Electrical Characteristics of Al
and the Effect of Postdeposition Annealing
Hai Dang Trinh, Yueh Chin Lin, Edward Yi Chang, Senior Member, IEEE, Ching-Ting Lee, Fellow, IEEE,
Shin-Yuan Wang, Hong Quan Nguyen, Yu Sheng Chiu, Quang Ho Luc, Hui-Chen Chang,
Chun-Hsiung Lin, Simon Jang, and Carlos H. Diaz, Fellow, IEEE
Abstract— The characteristics of Al2O3/InSb MOSCAPs processed with different postdeposition annealing (PDA) temperatures are investigated. X-ray photoelectron spectroscopy analysis shows a significant reduction of InSb-oxides after HCl plus trimethyl aluminum treatment and oxide deposition. Multifrequency capacitance-voltage (C–V ) characteristics exhibit low-frequency and asymmetrical C–V behaviors, in which capac-itance in the InSb conduction band side is lower than in the valence band side. The electrical properties of the MOSCAPs are sensitive to PDA temperature and degraded significantly at PDA temperature > 300 °C. This degradation is closely related to the diffusion of In, Sb into Al2O3as indicated by transmission electron microscopy analyses.
Index Terms— Al2O3, asymmetrical C–V , atomic layer depo-sition (ALD), InSb, MOS, post depodepo-sition annealing (PDA).
BESIDES the use in infrared imaging systems, high carrier mobility, narrow-gap InSb has drawn attention for its potential in extremely high-speed, low-power CMOS devices application such as nanowire, quantum well (QW) or band-to-band tunneling (T) field-effect-transistors (FETs). Among III–V compounds, InSb has the highest electron
Manuscript received December 17, 2012; revised February 2, 2013; accepted March 15, 2013. Date of current version April 18, 2013. This work was supported by the Taiwan National Science Council under Contract 101-2923-E-009-002-MY3 and Contract 99-2221-E-164-MY3.
H. D. Trinh was with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. He is currently with the Manufacturing Company Limited, Hsinchu Science Park, Hsinchu 300, Taiwan (e-mail: email@example.com).
Y. C. Lin, H. Q. Nguyen, Y. S. Chiu, and Q. H. Luc are with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: firstname.lastname@example.org; email@example.com; firstname.lastname@example.org; email@example.com).
E. Y. Chang is with the Department of Materials Science and Engineering and the Department of Electronic Engineering, National Chiao Tung Univer-sity, Hsinchu 300, Taiwan (e-mail: firstname.lastname@example.org).
C.-T. Lee is with Department of Electrical Engineering, National Cheng Kung University, 01 University Road, Tainan 701, Taiwan (e-mail: email@example.com).
S.-Y. Wang is with the Department of Electronic Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: firstname.lastname@example.org).
H.-C. Chang, C.-H. Lin, S. M. Jang, and C. H. Diaz are with the Taiwan Semiconductor Manufacturing Company Limited, Hsinchu Science Park, Hsinchu 300, Taiwan (e-mail: email@example.com; firstname.lastname@example.org; email@example.com; firstname.lastname@example.org).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2013.2254119
mobility of 7.7 × 104 cm2V−1s−1 and hole mobility of 840 cm2V−1s−1 , which promise of both n- and p-channel high-performance transistors. InSb-based QWFETs demonstrated very-high speed performance at low supply voltage (0.5 V) for both n- and p-channels devices , . The integration of InSb on Si for MOS devices application was also reported . For both infrared and CMOS applications, the deposition of dielectric layer with good quality interfacial properties is essential for the effective performance of devices. Several methods such as anodic oxidation, plasma-enhanced chemical vapor deposition (PECVD), remote PECVD, and low-temperature chemical vapor deposition are used to deposit the insulator/oxide layer on InSb for studying. However, the study of InSb MOS capacitors (MOSCAPs) using atomic layer deposition (ALD) oxide is still seldom –. The ALD method is well known to be a robust and manu-facturable process, which is promising for manufacturing of CMOS technology. Because InSb has low thermal budget , the electrical characteristics of the ALD oxide/InSb MOSCAPs are sensitive to thermal processes. In this paper, the electrical properties of ALD Al2O3/InSb MOSCAPs and their
dependent on postdeposition annealing (PDA) temperatures are studied. The multifrequency asymmetrical C–V behavior of Al2O3/n-InSb MOSCAPs due to the low density of state
(DOS) in InSb conduction band is experimentally observed in this paper. The out diffusion of In, Sb atoms into Al2O3
is found to be the major effect on the electrical degradation of the MOSCAPs such as hysteresis, frequency dispersion,
C–V modulation, C–V stretch-out, and interface density of
II. MATERIALS ANDEXPERIMENT
Wafers used in this research are InSb (100) undoped sub-strate, naturally n-type behavior with donor concentration of 2.2 × 1016 cm−3 at room temperature, determined by Hall measurement. The wafers are initially degreased by rinsing in acetone and isopropanol for 2 min each. The samples are dipped in the diluted HCl 4% solution for 2 min, rising in deionized water, and blown dry by N2 gas. The samples are
then loaded into ALD chamber (Cambridge NanoTech Fiji 202 DSC) within 5 min after cleaning. In ALD chamber, the samples are precleaned by using ten pulses of trimethyl alu-minum (TMA)/Ar – before the deposition of 85 cycles
Fig. 1. (a) In 3d5/2 and (b) Sb 3d plus O1s XPS spectra of native InSb surface and 1.5-nm Al2O3/InSb interface.
(∼7.5 nm) Al2O3 at 250 °C, using TMA and H2O as
pre-cursors. The HCl plus TMA treatment is proved to improve effectively Al2O3/InAs interface , . The effect of TMA
treatment in the reduction of InSb native oxides is also reported . The samples are PDA at different temperatures of 300 °C, 350 °C, and 400 °C in N2 for 30 s. Ni/Au metal
gate is formed via photolithography/e-beam evaporation/liftoff process. Finally, Au/Ge/Ni/Au is deposited for backside ohmic contact followed by postmetal annealing at 250 °C in N2 for
30 s. The multifrequency C–V is measured by an HP4284A LCR meter. The quasistatic C–V (QSCV) curves are per-formed using an Agilent B1500A semiconductor device ana-lyzer. The chemical and structural properties of Al2O3/InSb
interface are studied by X-ray photoelectron spectroscopy (XPS) measurement using a commercial Microlab 350 XPS system and transmission electron microscopy (TEM) using a Philips Tecnai F-20 microscope with energy-dispersive X-ray spectroscopy (EDS) analysis.
III. RESULTS ANDDISCUSSION
Fig. 1 shows In 3d5/2 and Sb 3d plus O 1 s XPS spectra
of native InSb surface and the 1.5-nm ALD Al2O3/HCl plus
TMA-treated InSb interface. The O 1 s peak overlapped with the Sb 3d5/2-related oxides peak. After surface treatment
and oxide deposition, In-oxides are reduced significantly as shown in In 3d5/2 spectra [Fig. 1(a)]. The Sb 3d3/2
spec-tra in Fig. 1(b) show the reduction of Sb-related oxides below the XPS detection level. The O 1 s plus oxidized Sb 3d5/2 peak originally assigned to O–Sb and O–In bonds
shifted to higher binding energy, which is mostly attributed to Al–O bonds. Similar O 1s peak position corresponding to Al–O bonds is also obtained by in situ XPS measurement of 1-nm ALD Al2O3/ammonium sulfide-treated InSb .
Fig. 2(a) shows the typical C–V behavior of the MOSCAPs at frequency of 1 MHz. The observed low-frequency C–V response at high frequency of 1 MHz is due to the high intrin-sic carrier density ni in InSb material [ni ∼ 2 × 1016 cm−3 at
Fig. 2. (a) Typical low-frequency asymmetrical C–V response at 1 MHz. (b) Typical multifrequency C–V responses of Al2O3/InSb MOSCAP structure.
PARAMETERS OFInSb USED IN(1) 
tTn (s) tTp (s) ND (cm−3) ni (cm−3) NC (cm−3) NV (cm−3) 5× 10−8 5× 10−8 2.2 × 1016 2× 1016 4.2 × 1016 7.3 × 1018
room temperature (RT)] . The relation between ni and the
minority carrier response timeτR is given by 
τR= 1 √ 2 ND ni τT 1−υT uB 1/2 (1) where ND is donor doping density, τT = √τTnτTp (τTn and τTp are bulk electron and hole life times), υT and uB are
potentials above the intrinsic level of bulk trap and Fermi levels in InSb . By taking the parameters in Table I , the value ofτR in InSb estimated by (1) is of 3.9 × 10−8s at
room temperature. This very short response time would allow minority carriers to response to such high-frequency ac signal as 1 MHz.
The asymmetrical C–V curve, in which the capacitance on the InSb conduction band side is lower than on the valence band side, is also observed obviously in Fig. 2(a). To our knowledge, this observation is first time witnessed by exper-imental high-frequency C–V measurement. The observation at high frequency of 1 MHz is due to the observation of low-frequency C–V response in InSb-based MOSCAPs as
Fig. 3. (a) C/Cmax− V . (b) Normalized C–V characteristics at 1 MHz of the Al2O3/InSb MOSCAPs with different PDA temperatures. (c) Frequency dispersion, hysteresis. (d) Interface trap profiles of the MOSCAPs increase significantly at PDA temperature greater or equal to 350°C.
discussed above and a very low DOS in InSb conduction band (NC). At RT, the value of NCis 4.2×1016cm−3, which is
170-fold lower than NV (7.3 × 1018 cm−3) . This low value of NCwould lead to the semiconductor capacitance Cs could not
be very large compared with oxide capacitance Cox, and thus
results in lower the total capacitance Ctot in the conduction
band side according to the following equation :
Ctot= Cox 1+ Cox Cs+ Ctr −1 (2) where Ctr is capacitance by the traps at/near Al2O3/InSb
The typical multifrequency C–V response of Al2O3/InSb
MOSCAPs is shown in Fig. 2(b). At low frequency, the asymmetrical C–V behavior becomes less significant that implies the increase of the contribution of Ctr to the Ctot with
the decrease of the measuring frequency [see (2)]. For narrow gap semiconductor as InSb, the interface traps response time is so short that it can follow the ac signal with frequency in the range 1 kHz to 1 MHz . In this context, the increase of Ctr with the decrease of measuring frequency might come
from the interaction of traps located inside oxide (called border traps) with conduction band electrons via tunneling .
Fig. 3 shows the comparison of samples underwent various PDA temperatures. The C/Cmax–V responses at 1 MHz of
samples are shown in Fig. 3(a). The modulation of C–V curves is less significant with the increase of the PDA temperatures. Fig. 3(b) and (c) shows the increase significantly of C–V stretch-out, frequency dispersion, and hysteresis when the PDA temperature is greater than or equal to 350 °C. The
C–V stretchout is caused by the slow interface/border traps
that could not follow the ac signal but do follow the dc bias sweep . The degradation of C–V stretchout is significant
in the negative gate bias side [Fig. 3(b)] shows a noticeable increase of the donor-like interface/border traps at the PDA temperature of 350 °C and above. To quantify the degradation, the interface traps are extracted by low-frequency C–V fitting method by self-consistent solution of Schrodinger–Poisson equations, similar to the approach in  and . Initially, the semiconductor capacitance CS is extracted by solving the
Schrodinger–Poisson equations of the Al2O3/InSb ideal MOS
structure (without interface density). The capacitance due to interface traps of the real MOS structure (Cit) is calculated by
from the following equation :
CoxCmes Cox− Cmes − CS
(3) where, Cox is the oxide capacitance and Cmes is experimental
QSCV data. From this value, the simulated C–V curve is extracted and compared again with the experimental C–V curve. Some parameters of the MOS structures such as flat band voltage (Vfb) and charge neutral level (ECNL) are
modulated by the simulation and the Dit profile is extracted
when the best fit between simulating and experimental C–V is occurred. The traps energy level E is defined from the equation , 
E− EC = Eg+ EF− qϕs (4)
where EC, Eg, and EF are conduction band minimum level,
band gap, and Fermi level in InSb, respectively, and ϕs is
surface potential. The surface potential is determined from the gate bias Vg given by
ϕs = Vg− Vfb+
Qs+ Qit Cox
(5) where Qs and Qit are the semiconductor charge and interface
Fig. 4. TEM images of the Al2O3/InSb structures. (a) After oxide deposition. (b) PDA at 300°C, 30 s. (c) PDA at 350°C, 30 s. (d) EDS spectra of the samples.
samples without PDA and PDA at 300 °C with minimum value of 2.55 × 1012 eV−1cm−2 at trap position E–EV =
0.275 eV as shown in Fig. 3(d). Simultaneously, the minimum of Dit levels of the samples which went through PDA at
350 and 400 °C increases significantly with increasing PDA temperatures.
The high-resolution transmission electron microscopy analyses of 7.5-nm Al2O3/InSb as dep, PDA at 300 °C and
350 °C are shown in Fig. 4 (the TEM figure of the sample PDA at 350 °C is the spotted through the use of Pt for preventing the sample’s damage). From the high-resolution cross-sectional TEM image in Fig. 4(a), it is clearly shown that the as deposited sample exhibits a double-layer gate oxide with thickness of 1.5 nm/6 nm. The 1.5-nm layer is attributed to the out diffusion of In, Sb into Al2O3 during the 1 h suffered
at 250 °C oxide deposition process. The out-diffusion layer increases with the increasing of PDA temperatures as indicated in Fig. 4(a)–(c). The EDS analysis of the samples shown in Fig. 4(d) also indicates the increase of In, Sb out-diffusion into Al2O3 with the increasing of PDA temperatures. This strong
out-diffusion would result in the degradation of Al2O3/InSb
interface as well as Al2O3 oxide itself, which leads to the
degradation of the electrical properties of the MOSCAPs as discussed above.
In conclusion, we discussed the electrical properties of Al2O3/InSb MOSCAPs and their dependent on PDA
temperature. The low-frequency asymmetrical C–V behavior was experimentally observed at high-frequency C–V mea-surement because of the short minority carrier response time and low DOS in InSb conduction bandgap. When the PDA temperature was increased to 350 °C and above, the electri-cal properties of the MOSCAPs degraded significantly. This degradation was due to the strong out diffusion of In, Sb atoms into the Al2O3 oxide layer with the increase of PDA
temperature proved by TEM and EDS analyses. REFERENCES
 M. Levinshtein, S. Rumyantsev, and M. Shur, Handbook Series on
Semiconductor Parameters. Singapore: World Scientific, 1996.
 S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. J. Phillips, D. Wallis, P. Wilding, and R. Chau, “85 nm Gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications,” in Proc. IEEE Int. IEDM Tech. Dig. Electron
Devices Meeting, Dec. 2005, pp. 763–766.
 M. Radosavljevic, T. Ashley, A. Andreev, S. D. Coomber, G. Dewey, M. T. Emeny, M. Fearn, D. G. Hayes, K. P. Hilton, M. K. Hudait, R. Jef-feries, T. Martin, R. Pillarisetty, W. Rachmady, T. Rakshit, S. J. Smith, M. J. Uren, D. J. Wallis, P. J. Wilding, and R. Chau, “High-performance 40 nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5 V) logic appli-cations,” in Proc. IEEE Int. IEDM Electron Dev. Meeting, Dec. 2008, pp. 727–730.
 A. Kadoda, T. Iwasugi, K. Nakatani, K. Nakayama, M. Mori, K. Maezawa, E. Miyazaki, and T. Mizutani, “Characterization of Al2O3/InSb/Si MOS diodes having various InSb thicknesses grown on Si(1 1 1) substrates,” Semicond. Sci. Technol., vol. 27, no. 4, pp. 045007-1–045007-6, Feb. 2012.
in atomic layer deposition of Al2O3 on InSb,” J. Electrochem. Soc., vol. 155, no. 9, pp. G180–G183, Jul. 2008.
 H.-Y. Chou, V. V. Afanas’ev, M. Houssa, A. Stesmans, L. Dong, and P. D. Ye, “Electron band alignment at the interface of (100)InSb with atomic-layer deposited Al2O3,” Appl. Phys. Lett., vol. 101, no. 8, pp. 082114-1–082114-3, Aug. 2012.
 H.-S. Kim, I. Ok, M. Zhang, F. Zhu, S. Park, J. Yum, H. Zhao, J. C. Lee, P. Majhi, N. Goel, W. Tsai, C. K. Gaspe, and M. B. Santos, “A study of metal-oxide-semiconductor capacitors on GaAs, In0.53Ga0.47As, InAs, and InSb substrates using a germanium interfacial passivation layer,” Appl. Phys. Lett., vol. 93, no. 6, pp. 062111-1–062111-3, Aug. 2008.
 H.-D. Trinh, E. Y. Chang, Y.-Y. Wong, C.-C. Yu, C.-Y. Chang, Y.-C. Lin, H.-Q. Nguyen, and B.-T. Tran, “Effects of wet chemical and trimethyl aluminum treatments on the interface properties in atomic layer deposition of Al2O3on InAs,” Jpn. J. Appl. Phys., vol. 49, no. 11, pp. 111201-1–111201-4, Nov. 2010.
 H. D. Trinh, G. Brammertz, E. Y. Chang, C. I. Kuo, C. Y. Lu, Y. C. Lin, H. Q. Nguyen, Y. Y. Wong, B. T. Tran, K. Kakushima, and H. Iwai, “Electrical characterization of Al2O3/n-InAs metal-oxide-semiconductor capacitors with various surface treatments,” IEEE Electron Device Lett., vol. 32, no. 6, pp. 752–754, May 2011.
 H. D. Trinh, E. Y. Chang, P. W. Wu, Y. Y. Wong, C. T. Chang, Y. F. Hsieh, C. C. Yu, H. Q. Nguyen, Y. C. Lin, K. L. Lin, and M. K. Hudait, “The influences of surface treatment and gas annealing conditions on the inversion behaviors of the atomic-layer-deposition Al2O3/n-In0.53Ga0.47As metal-oxide semiconductor capac-itor,” Appl. Phys. Lett. vol. 97, no. 4, pp. 042903-1–042903-3, Jul. 2010.
 D. M. Zhernokletov, H. Dong, B. Brennan, J. Kim, and R. M. Wallace, “In situ X-ray photoelectron spectroscopy characterization of Al2O3/InSb interface evolution from atomic layer deposition,” Appl.
Surf. Sci., vol. 258, no. 14, pp. 5522–5525, Feb. 2012.
 E. H. Nicollian and J. R. Brews, Metal Oxide Semiconductor Physics
and Technology. New York, NY, USA: Wiley, 1982.
 Y. Yu, W. Lingquan, Y. Bo, S. Byungha, A. Jaesoo, P. C. McIntyre, P. M. Asbeck, M. J. W. Rodwell, and T. Yuan, “A distributed model for border traps in Al2O3–InGaAs MOS devices,” IEEE Electron Device
Lett., vol. 32, no. 4, pp. 485–487, Apr. 2011.
 C.-W. Cheng, G. Apostolopoulos, and E. A. Fitzgerald, “The effect of interface processing on the distribution of interfacial defect states and the C-V characteristics of III-V metal-oxide-semiconductor field effect transistors,” J. Appl. Phys., vol. 102, no. 2, pp. 023714-1–023714-8, Jan. 2011.
 M. M. Satter, A. E. Islam, D. Varghese, M. A. Alam, and A. Haque, “A self-consistent algorithm to extract interface trap states of MOS devices on alternative high-mobility substrates,” Solid-State Electron., vol. 56, no. 1, pp. 141–147, Feb. 2011.
 H. Q. Nguyen, H. D. Trinh, E. Y. Chang, C. T. Lee, S. Y. Wang, H. W. Yu, C. H. Hsu, and C. L. Nguyen, “In0.5Ga0.5As-based metal-oxide-semiconductor capacitor on GaAs substrate using metal-organic chemical vapor deposition,” IEEE Trans. Electron Devices, vol. 60, no. 1, pp. 235–240, Jan. 2013.
 D. K. Schroder, Semiconductor Material and Device Characterization. New York, NY, USA: Wiley, 2006.
Hai Dang Trinh received the Ph.D. degree from National Chiao Tung University, Hsinchu, Taiwan, in 2011.
He is currently with the Specialty Module Divi-sion, Taiwan Manufacturing Company Limited, Hsinchu Science Park, Hsinchu.
Taiwan, in 2000.
He is currently a Post-Doctoral Researcher with the Compound Semiconductor Device Laboratory, Department of Materials Science and Engineering, NCTU.
Edward Yi Chang (S’85–M’85–SM’04) received the Ph.D. degree from the University of Minnesota, Minneapolis, MN, USA, in 1985.
He is currently the Dean of Office of Research and Development, National Chiao Tung University, Hsinchu, Taiwan.
Ching-Ting Lee (F’09) received the Ph.D. degree from Carnegie-Mellon University, Pittsburgh, PA, USA, in 1982.
He is currently a Professor with the Institute of Microelectronics, Department of Electrical Engi-neering, National Cheng Kung University, Tainan, Taiwan.
Shin-Yuan Wang is currently pursuing the Ph.D. degree with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan.
Hong Quan Nguyen received the Ph.D. degree in materials science and engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2012.
He is currently a Post-Doctoral Researcher with the Department of Materials Science and Engineer-ing, NCTU.
Yu Sheng Chiu is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu, Taiwan.
Quang Ho Luc is currently pursuing the Ph. D. degree with the Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu, Taiwan.
Hui-Chen Chang is currently a Senior Manager with the Advanced Tech-nology Module Division, Taiwan Semiconductor Manufacturing Company, Hsinchu Science Park, Hsinchu.
Chun-Hsiung Lin received the Ph.D. degree in materials science and engineering from the Univer-sity of Illinois at Urbana-Champaign, Urbana, IL, USA, in 2000.
He is currently a Manager with Taiwan Semicon-ductor Manufacturing Company, Hsinchu Science Park, Hsinchu, Taiwan.
Simon Jang currently a Director of Advanced Technology Module Division, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science Park , Hsinchu, Taiwan.
Carlos H. Diaz (F’08) received the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, Urbana, IL, USA.
He is currently the Director of Advanced Device Technology, Taiwan Semiconductor Manufacturing Company, Hsinchu Science Park, Hsinchu, Taiwan.