A 1-V 50-MHz Pseudodifferential OTA With
Compensation of the Mobility Reduction
Tien-Yu Lo, Student Member, IEEE, and Chung-Chih Hung, Senior Member, IEEE
Abstract—This brief presents a high-linearity operational
transconductance amplifier (OTA) based on pseudodifferential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down to achieve high speed operation. Transconductance tuning could be achieved by a MOS operating in the linear region. The OTA fabricated in the 0.18- m CMOS process occupies a small area of4 5 10 3mm2. The measured third-order intermodulation (IM3) distortion with a 400 mV differential input under 1-V power supply voltage remains below 52 dB for frequency up to 50 MHz. The static power consumption is 2.5 mW. Experimental results demonstrate the agreement with theoretical analyses.
Index Terms—Low supply voltage, operational
transconduc-tance amplifier (OTA), strong inversion region, subthreshold region, transconductance tuning.
I. INTRODUCTION
T
HE CIRCUIT that converts the voltage applied to the input terminals into current at output nodes is generally referred as a – converter or an Operational Transconductance Am-plifier (OTA). The OTA is a basic building block in analog VLSI applications, including continuous-time filters [1]–[3] and four-quadrant multipliers [4]. The precision of the data signal processing is limited by the performance of the linearity and noise. There are numerous previous works to improve the OTA linearity [6]. On one hand, with the reduction of power supply voltage, the operating range is decreased. On the other hand, linearity based on the MOS transconductance or saturated square-law behavior becomes worse in the sub-micron process owing to the appearance of short-channel effects. The combina-tion of linearizacombina-tion techniques has been used recently [7]–[9], but the potential of getting higher power consumption makes the combined linearity mechanism less practical. Therefore, maintaining high linearity while also achieving high speed becomes very challenging under the conditions of low power supply voltage and limited power consumption.This brief presents a highly linear OTA in 1-V power supply voltage and is organized as follows. The design issues and cir-cuit details are discussed in Section II. Compensation of the non-linearity is also analyzed in this section. The experimental re-sults are presented in Section III. Finally, Section IV concludes the brief.
Manuscript received December 19, 2006; revised April 14, 2007. This work was supported by National Science Council of Taiwan. This paper was recom-mended by Associate Editor P. P. Sotiriadis.
The authors are with the Department of Communication Engineering, National Chiao Tung University, Hsinchu, 30050 Taiwan, R.O.C. (e-mail: [email protected]).
Digital Object Identifier 10.1109/TCSII.2007.907559
Fig. 1. Nolinearity cancellation mechanism.
Fig. 2. (a) Basic pseudodifferential CMOS pair. (b)Mobility compensation in the pseudodifferential structure.
II. PROPOSEDTRANSCONDUCTORCELL
Fig. 1 shows the block diagram of the proposed approach. It is known that under the differential architecture, the third-order distortion of the OTA will be the dominant term of its nonlin-earity performance. Two voltage-to-current converters with the same first-order sign and opposite third-order sign are provided in the OTA. Therefore, the nonlinearity term of the OTA can be reduced with the addition of the two transconductance.
A. Mobility Compensation
The circuit implementation of the block diagram is based on the fact that transistors working in the saturation and sub-threshold regions have opposite signs of the third-order har-monic distortion. Fig. 2(a) shows the basic pseudodifferential CMOS pair. When transistors M1a and M1b operate in the sat-uration region, the effective carrier mobility would be the
1048 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 12, DECEMBER 2007
tion of longitudinal and transversal electric fields due to short-channel effects. The drain current can be approximated as
(1) where and are the width and length of the device, re-spectively, is the oxide capacitance per unit channel area, is the low-field mobility, is the mobility reduction coef-ficient, is the nMOS threshold voltage (a typical value of 0.43 V in the adopted process), and is the output impedance constant. By taking nonlinear effects into accounts of the satu-rated device, the differential output current can be expanded by Taylor series and obtained as follows:
(2) where equals to and the even-order harmonic distortion terms are cancelled out due to the topology of the differential structure. The third-order harmonic distortion term of the saturated transistors can be calculated as
(3) where is the input common-mode voltage. The above equation is inversely proportional to the input common-mode voltage, so the third-order harmonic distortion term increases rapidly for low power supply voltage. On the other hand, the drain current of the subthreshold transistors can be expressed as (4) where and are the width and length of the device, re-spectively, is the process-dependent parameter, is the sub-threshold slope factor, and is the thermal voltage. When transistors M1a and M1b work in the subthreshold region, the coefficient of the third-order harmonic distortion term of the dif-ferential output current would be given by
(5) The third-order harmonic distortion term would be decreased by smaller device width and smaller input common-mode voltage. As the current of the saturated transistor is combined with that of the subthreshold transistor, the nonlinearity term can be reduced by choosing proper aspect ratios such that
(6) Fig. 2(b) shows the implementation of the concept. Transis-tors M1, M2, and M3 are working in the saturation region. The source follower composed by M2 and M3 is used to force M4 to enter the subthreshold region. Thus, the third-order nonlinear term could be reduced by given
(7) where is inversely proportional to the gain of the source follower. Therefore, the third-order harmonic distortion term
would be cancelled out by adding drain current of M1 and M4 together. Since transistor M4 needs to work in the subthreshold region in order to reduce the harmonic distortion, the source follower plays an important role in the approach. For large bias current, the gate–source voltage of the source follower will become larger. In this case, the minimum input swing range and the aspect ratio of transistor M4 should be increased in order for M4 to stay in the subthreshold region and for effective nonlinearity compensation. If a smaller source follower gain is maintained, the source follower would work as a voltage at-tenuator and the input swing range can be increased. However, under this condition, the compensation ability of the third-order harmonic distortion provided by the subthreshold transistor M4 will become weaker due to a higher attenuation ratio. Therefore, the aspect ratios of transistors M2, M3, and bias current, set by voltage , should be optimized. In order to maintain proper circuit operation, the minimum input swing range is set by the condition that transistors M1 and M4 work in their respectively specified regions, which is given by , where is the gate–source voltage of the transistor M2 and is the drain-source voltage of the transistor M3. We should note that owing to transistor M4 working in the sub-threshold region, the input swing limit is caused by the correct operation of the source follower, and the of transistor M3 should be taken into consideration. On the other hand, when the operation region of transistor M4 is maintained, the maximum input voltage is limited due to the low power supply
voltage, which is given by ,
where is the voltage drop at loading transistors.
The linearity performance of the input signal will also be de-graded by the ideal effect of the source follower. The non-linearity term of nMOS source followers is dominated by the body effect [10]. The 0.18- m mixed-signal CMOS process is a deep n-well process, so the body of the nMOS source fol-lower can be connected to the source in a p-well to eliminate the body effect. However, mobility degradation and channel length modulation can also degrade the linearity performance of the source follower. The second-order distortion term of the source follower will be the dominant factor to affect the third-order har-monic distortion term in the drain current of subthreshold tran-sistors. In addition, such a level shifter adds a high frequency pole of little influence.
B. Proposed OTA Implementation
Fig. 3 shows the proposed OTA circuit. The optimal ratios between the two voltage-to-current converters have been estab-lished to achieve minimal harmonic distortion. In the circuit, the transistor MR connected between two current mirrors would be working in the linear region as a resistor. Therefore, the continuous tuning of the transconductance can be employed by adjusting the gate voltage, . The MOS resistor which acts as the attenuator actually promotes the linearity performance. In addition, it not only improves the linearity performance, but also adds a tuning strategy. Besides, the current mirror would introduce another high frequency pole, which is located at lower frequency than that caused by the source follower. The non-dom-inant poles would only slightly influence the excess phase in this approach. Fortunately, the speed limitation caused by current
Fig. 3. Proposed OTA circuit.
Fig. 4. Large-signal simulation of the proposed circuit.
mirror circuit would be relaxed by the addition of the small MOS resistor MR.
Fig. 4 illustrates the large-signal simulation of the proposed circuit. We can find that if no subthreshold transistors are used, the linearity performance is limited. When we increase the transconductance value of subthreshold transistors, high lin-earity performance can be obtained. However, if an even larger transconductance value of subthreshold transistors is used, the third-order harmonic distortion term would be dominated by the subthreshold transistors. Besides, simulation also indicates the unity-gain bandwidth of 200 MHz with a 2-pF loading and the phase margin of 89 are obtained.
In the pseudodifferential structure, in order to maintain low voltage operation, the use of stacked devices, such as the cas-code structure, is prohibited. Therefore, to maintain the high output resistance in the pseudodifferential structure under the sub-micron process, increasing channel length could be one so-lution. However, a very long-channel transistor will increase the parasitic capacitance associated with the output node, and thereby reduce the OTA bandwidth. In Fig. 3, as the aspect ratio of transistor M11 equals to that of M12 and M13 equals to M14, the saturated transistors give the following expressions for both the differential-mode resistance and common-mode resistance
(8)
where and are the small-signal transconductance of M11 and M13, respectively, and is the output resis-tance paralleled by the drain-source resisresis-tance of M11, M12, M13, M14, M15, and M16. By designing a little larger aspect value of M13 than M11, the negative conductance formed by – would be close to the value of so as to in-crease the overall differential output resistance. The differen-tial gain can be designed to a large value which will be suit-able for most of applications. Moreover, as we can obtain the common-mode resistance from (8), the common-mode stability would be guaranteed by providing larger aspect ratios of tran-sistors M11 and M13 than those of input trantran-sistors.
C. Nonidealities in the Proposed OTA
Mismatch between the input transistors of the OTA will cause an imbalance in the drain current of the current mirrors, and thus generate even-order harmonics in voltage-to-current con-version. A significant increase of the device size will reduce offset caused by random mismatch. Besides, the small MOS re-sistor helps to reduce the even-order harmonics by balancing the voltage at both terminals, and thus minimize the drain current mismatch caused by current mirrors. Therefore, with the MOS resistor, the dc offset caused by the device mismatch is reduced by allowing the load resistance seen from input transistors to be different. For the output stage, mismatch between transistors would limit the differential mode gain. Careful layout was taken where the device match is required.
The output noise current of the OTA is the combination of sat-urated and subthreshold input transistors, current mirrors, and the MOS resistor. In high speed circuit design, the most sig-nificant noise source of a single transistor is the thermal noise generated in the channel. The channel noise can be modeled by a current source connected between the drain and source with a spectral density [11]
(9) where is the Boltzmann constant, is the source conduc-tance, and the device noise parameter depends on the bias con-dition [11]. For the proposed circuit of the differential structure,
1050 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 12, DECEMBER 2007
Fig. 5. Die microphotograph.
we have defined , where equals to the odd number (ex: , ). Thus, the thermal noise density evaluated at the output node is derived as
(10) where , , and would be the noise parameter at saturation, subthreshold, and linear regions, respectively. Besides, is the resistance of linear region transistor MR. From noise anal-ysis, the source follower adds the input-referred noise while providing a voltage gain less than unity. Also, to reduce the thermal noise, the transconductance of input transistors should be maximized, which implies that an increasing overdrive input common-mode voltage would result in a higher signal-to-noise ratio (SNR).
III. EXPERIMENTALRESULTS
The chip was fabricated in 0.18- m deep n-well CMOS process. The micrograph of the chip is shown in Fig. 5 where the active area is . The device size of saturated transistors M1 and M2 is 6 m/0.18 m, the subthreshold transistors M9 and M10 is 1 m/0.18 m, the linear transistor MR is 15 m/0.18 m, and the bias voltage of is 0.6 V. A supply voltage of 1 V was employed in the measurements and the nominal static power consumption of the OTA is 2.5 mW. The output current versus input voltage over the tuning range is shown in Fig. 6. The measured harmonic distortion for a 400 mV differential input signal at 1 MHz is dB, and the third-order harmonic distortion of the output currents dominates the nonlinearity performance. The second-order harmonic distortion is due to the mismatch in the off-chip single-ended to differential input and differential output to single-ended conversion setup. The limitation of the input swing range is due to the departure of correct working regions under low power supply voltage as predicted theoretically. The third-order intermodulation (IM3) distortion measured with two sinusoidal tones of 400 mV amplitude
Fig. 6. Output current versus input voltage over the tuning range.
Fig. 7. Measured two tone intermodulation distortion.
is shown in Fig. 7. The IM3 is shown to be less than dB at the speed of 50 MHz and drops to dB at 56 MHz. The measured input referred noise spectral density at 50 MHz is 13 nV Hz. Table I summarizes the performance of this work with recently reported OTAs.
IV. CONCLUSION
A novel pseudodifferential OTA based on a mobility compen-sation technique has been fabricated and measured. It is based on the principle that the third-order harmonic distortion term could be cancelled by the addition of the two drain current, one in the saturation region and the other in the subthreshold region, applying small extra power consumption by adding the linearity enhancement stage. The technique employed leads to a signifi-cant increase of linearity performance in the voltage-to-current conversion. The measurement results show less than dB IM3 at 50-MHz input signal under 1-V power supply voltage. We can conclude that the low-voltage OTA could be provided as
TABLE I
COMPARISON OFPREVIOUSLYREPORTEDWORKS
a high linearity and high speed building block in analog VLSI applications.
ACKNOWLEDGMENT
The authors would like to thank the National Chip Implemen-tation Center of Taiwan for supporting the chip fabrication.
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