IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 21, NO. 9, SEPTEMBER 2011 489
A 78
102 GHz Front-End Receiver
in 90 nm CMOS Technology
Hsuan-Yi Su, Robert Hu, and Chung-Yu Wu
Abstract—In this letter, a 78 102 GHz front-end receiver de-signed in 90 nm CMOS technology is presented. It consists of an ultra-wideband low-noise amplifier, a subharmonic mixer, and an IF buffer. This receiver has a peak gain of 11.8 dB at 94 GHz with the noise figure of 13.4 dB. The measured input-referred 1 dB com-pression point is 14.5 dBm and the total power dissipation is 18.6 mW. The chip size is680 1020 m2.
Index Terms—CMOS receiver, low noise amplifier (LNA), sub-harmonic mixer, ultra wideband (UWB), W-band.
I. INTRODUCTION
M
ILLIMETER-WAVE receivers have been widely used in applications such as radars, radiometers and scientific instrumentations. Recently, we have seen the surging of novel 60 GHz silicon-integrated circuits proposed for high definition multi-media interface (HDMI), and their prototypical commer-cial products are also presented [1]–[7]. This, therefore, prompts us to the challenge of using similar process technology to design an even higher 78 102 GHz receiver circuit so that both re-liability and affordability can be achieved for W-band data and multimedia communications, either narrow-band or wideband, in the near future.Designed in 90 nm CMOS technology, the proposed receiver is made of three sub-circuits: the first is an ultra-wideband low noise amplifier (LNA), the second is a subharmonic mixer with wide intermediate frequency (IF), and the last is an open-drain IF buffer to facilitate direct measurement. As shown in Fig. 1, the incoming millimeter-wave signal is sent to a matched three-stage LNA first. The amplified 78 86 GHz RF signal is then transformed to its IF counterpart when the local-oscillation (LO) frequency of the subharmonic mixer is set to 39 GHz. By setting the LO to 43, 47, and 51 GHz, respec-tively, the 86 94 GHz, 94 102 GHz, and 102 110 GHz RF signals can be down-converted consecutively. The proposed receiver demonstrates comparable performance with other re-ceivers designed in more advanced process technologies [8], [9], but it has a wider bandwidth and consumes less power. Descrip-tion of the LNA, mixer, and IF buffer as well as measurement results will be given in the following.
Manuscript received January 14, 2011; revised May 28, 2011; accepted July 06, 2011. Date of publication August 12, 2011; date of current ver-sion September 02, 2011. This work was supported in part by the National Science Council of Taiwan under Contracts NSC-97-2221-E-009-179, 97-2220-E-009-045, and 98-2220-E-009-033.
The authors are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: hillo.ee91g@nctu.edu. tw).
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LMWC.2011.2162940
Fig. 1. Block diagram of the W-band receiver. With 39 GHz LO, the 78 86 GHz RF is transformed to theDC 80GHz IF. When the LO is shifted to 43, 47, and 51 GHz, respectively, the 86 94 GHz, 94 102 GHz and 102 110 GHz RF signals can be down-converted consecutively.
Fig. 2. Schematic of the LNA. The inductorL is used to resonate out the gate-drain capacitor of transistorM .
II. CIRCUITDESIGN
The schematic of the CMOS W-band LNA is shown in Fig. 2. It is composed of three common-source amplifying stages where the frequency for maximum gain in each stage is set at three different frequency points. Thus overall band-width in the LNA design can cover 78–102 GHz. To obtain a nearly flat gain over the bandwidth, the maximum gain of each stage is kept almost the same, which is around 18 dB in post-layout simulation. All the transistors in Fig. 2 are made of three 2 m-wide 80 nm-long fingers, with the corresponding unity-gain (cutoff) frequency being 144 GHz under drain bias voltage of 1.2 V and drain bias current of 3.2 mA.
The input matching circuit consists of a pad capacitor and a gate inductor . The minimum input reflection coeffi-cient occurs at around 95 GHz. As the first stage of the LNA needs to reach its maximum gain at a very high frequency, a feedback inductor is inserted between the drain and gate nodes of the transistor so as to resonate its gate-drain capaci-tance and boost its gain performance at 100 GHz and above. Since the maximum-gain frequencies of 92 GHz and 75 GHz designated for the second and third stages, respectively, are well below of 144 GHz, no such inductor is needed, and therefore
490 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 21, NO. 9, SEPTEMBER 2011
Fig. 3. Schematic of the subharmonic mixer and IF buffer.
compact chip size can be retained. Through the drain inductor and , the gate bias voltages of and can be set to the system voltage , respectively. Thus extra gate bias circuits and the inter-stage DC-blocking capacitors can be avoided to completely remove their effects on the gain degrada-tion.
Fig. 3 shows the subharmonic mixer used in the proposed re-ceiver where the RF signal is connected to the gate nodes of the mixing transistors and , the LO is applied to their source nodes, and the down-converted IF is extracted from the common drain node. Mathematically, the LO modulated transconduc-tance can be expressed as
where is the LO frequency. The down-converted upper-side-band IF voltage can be derived as
where and are the voltage and frequency of the ap-plied RF signal, respectively. The desired IF signal is selected by the low-pass output characteristics of the mixer cir-cuit in Fig. 3. The center-tapped inductor is used to resonate the parasitic source capacitance of and . Thus a high input impedance between 39 51 GHz at the LO port can be achieved. In Fig. 3, the three DC-blocking capacitors are 200 fF, the two gate bias resistors are 5 , and the drain bias resistor is 3 . The post-layout simulation results show that the proposed mixer has a gain of 3.8 dB. The buffer transistor with its drain node connected to an external bias-Tee is used to facilitate the measurement. Photograph of the receiver chip is shown in Fig. 4.
III. MEASUREMENTRESULTS
In the measurement setup shown in Fig. 5, the W-band source module (Agilent S10MS-AG) is used to shift the frequency of the RF signal from the signal generator (Agilent E8257D) to the W-band. The W-band attenuator is used to adjust the cor-responding power level and its output is connected to the chip through the adapter (WR-10) and cable. The 180-degree hybrid power divider is used to generate the differential LO signals.
Fig. 4. Photograph of the W-band CMOS receiver chip. The chip size is6802 1020 m .
Fig. 5. Measurement setup for the fabricated W-band CMOS receiver.
As mentioned, a bias-Tee (Anritsu V255) is connected to the IF output of the fabricated chip to allow direct measurement using a network analyzer (Agilent 8510C) or spectrum ana-lyzer (Agilent E4448A). To calibrate the power loss of RF input signal to the chip under test, a self-calibrated W-band harmonic mixer (Agilent 11970W) is used to measure the input RF power through the cable before the chip measurement. Thus the power loss is calibrated and it does not affect the measured results.
The measured gain and noise figure are shown in Fig. 6, where a fixed 39 GHz LO is employed to obtain the 78 86 GHz RF response. By moving the LO frequency to 43, 47, and 51 GHz, respectively, the 86 94 GHz, 94 102 GHz and 102 110 GHz RF responses can be successively mea-sured. The low (high) boundary of 1 dB gain ripple is at 80 GHz (96 GHz) where the gain is 10.6 dB (11.4 dB) and the noise figure is 14 dB (12.7 dB). At a much higher fre-quency, discernible performance degradation is observed in the measurement, which can be attributed to the uncertainties of both active and passive device modeling [10]. Fig. 7 shows the measured input reflection coefficient at the RF port. It can be seen that is smaller than 5 dB between 85 102 GHz and it can be as low as 19 dB at 94 GHz. To achieve the broadband matching where is kept low over a wide bandwidth, a more complicated input matching circuit considering the effect of is required. The input-referred 1 dB compression point, i.e., P1 dB, of the fabricated receiver
SU et al.: 78 102 GHz FRONT-END RECEIVER 491
Fig. 6. Measured gain and noise figure of the fabricated receiver. The gain is 10.6 dB (11.4 dB) and the noise is 14 dB (12.7 dB) at 80 GHz (96 GHz).
Fig. 7. Measured input reflection coefficientjS j at the RF port. Between 85 102 GHz, S is small than05 dB. Between 89 97 GHz, S is smaller than010 dB.
Fig. 8. Measured output IF power versus input RF power where the input-re-ferred P1 dB is014.5 dBm at 93 GHz.
at 93 GHz is 14.5 dBm, as determined from Fig. 8. The performance comparison with other W-band CMOS receivers is given in Table I where the values of power dissipation for all the receivers includes those of LNA and mixer only. The proposed receiver in 90 nm CMOS technology rather than the more advanced 65 nm CMOS technology, has a slightly larger noise figure. However, it has a much wider RF and IF bandwidth while consuming only 14.4 mW. When the IF buffer is taken into account, the total power consumption of the proposed receiver is 18.6 mW.
TABLE I
PERFORMANCECOMPARISON OFW-BANDCMOS RECEIVERS
These values only include the power dissipation of LNA and mixer for a fair comparison.
IV. CONCLUSION
In this letter, a W-band CMOS front-end receiver is presented. It has been successfully designed and measured in 90 nm CMOS technology. The receiver is made of an ultra-wide-band three-stage LNA, a subharmonic mixer, and an IF buffer. With 8 GHz IF bandwidth, it can easily cover the frequency range of 78 102 GHz by shifting the LO signal in steps. The proposed re-ceiver has a peak gain of 11.8 dB at 94 GHz with noise figure of 13.4 dB. The total power consumption is 18.6 mW.
ACKNOWLEDGMENT
The authors wish to thank the staff of the Chip Implementa-tion Center (CiC) and the NaImplementa-tional Nano Device Laboratories (NDL), Hsinchu, Taiwan, for assistance on chip fabrication and on-wafer measurement.
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