A Fully Integrated Built-In Self-Test
Σ
−
Δ
ADC
Based on the Modified Controlled
Sine-Wave Fitting Procedure
Hao-Chiao Hong, Member, IEEE, Fang-Yi Su, and Shao-Feng Hung, Student Member, IEEE
Abstract—This paper demonstrates the first fully integrated built-in self-test (BIST)Σ−Δ analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) com-prises a second-order design-for-digital-testabilityΣ−Δ modu-lator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and elimi-nate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13 300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST Σ−Δ ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT.
Index Terms—Analog-to-digital conversion (ADC), built-in self-test (BIST), design for self-testability, integrated circuit self-testing, mixed analog–digital integrated circuits,Σ−Δ modulation.
I. INTRODUCTION
A
S FABRICATION cost of modern mixed-signal IC keeps decreasing while testing cost does not, reducing high testing cost becomes a substantial issue for industry. The root causes of the high testing cost include expensive mixed-signal automatic test equipment (ATE), long test time, and ultralow noise testing environment [1]. To address high testing cost, many built-in self-test (BIST) techniques for mixed-signal cir-cuits have been proposed [2]–[17]. The functional-test-based BIST techniques are particularly appealing for analog-to-digital converters (ADCs) [2]–[4], [13], [14], [16]–[18]. The key idea is to embed the mandatory equipment of functional tests, in-cluding the analog stimulus generator (ASG) and the output response analyzer (ORA) on chip. Therefore, no costly mixed-signal ATE is needed. The test environment setup also becomesManuscript received May 26, 2009; revised September 5, 2009; accepted September 21, 2009. Date of publication December 15, 2009; date of current version August 11, 2010. This work was supported in part by the National Science Council, Taiwan, under Grant NSC97-2221-E-009-169-MY3 and in part by the Ministry of Economic Affairs, Taiwan, under Grant 95-EC-17-A01-S1-002. The Associate Editor coordinating the review process for this paper was Dr. John Sheppard.
The authors are with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIM.2009.2034582
easier because of the absence of off-chip analog signal paths. In addition, the BIST approaches could provide standard test results as conventional functional tests do because of their functional-test-based feature.
The major challenge of the BIST design is to implement the embedded high-precision ASG and ORA cost effectively. Jiang et al. proposed a deterministic dynamic element matching (DDEM) approach for digital-to-analog converters (DACs). With the DDEM, a low-resolution DAC can generate uniformly spaced voltage samples for testing ADCs [4]. Hence, the BIST hardware cost can be reduced.
Alternatively, we proposed a design-for-digital-testability (DfDT) structure for implementing digitally testable Σ−Δ modulators in [19]. During digital tests, the DfDT structure is reconfigured as a 1-bit digital-to-charge converter (DCC). The 1-bit DCC then takes aΣ−Δ modulated bitstream as the test stimulus and generates a nonlinearity-free analog stimulus. Consequently, the DfDT structure serves as the mandatory high-precision ASG very well. An additional advantage of the DfDT scheme is that the stimulus generation and the response analysis are performed by digital circuits. Thus, the BIST functions can be integrated with the analog core more conve-niently. Experimental results verified many advantages of the DfDT scheme, such as a small analog hardware overhead, high testing accuracy, high fault observability, and the capability of conducting at-speed tests.
Reference [20] demonstrates a BISTΣ−Δ ADC prototype using the same second-order DfDTΣ−Δ modulator in [19] as the modulator under test (MUT). The proposed BIST design in [20] is based on the controlled sine-wave fitting (CSWF) method [21]. A field-programmable gate array is used to im-plement the purely digital BIST circuits, including the digital stimulus generator (DSG) and the ORA. Experimental results show that the BIST signal-to-noise-and-distortion ratio (SNDR) results of the 1-kHz tone tests are almost the same as those obtained by the conventional fast Fourier transform (FFT) analysis [20]. However, several issues remain. First, the test bandwidth of the BIST prototype is less than 8 kHz. Second, the BIST results significantly differ from the corresponding FFT results for stimulus levels higher than −5 dBFS. Finally, the prototype is not fully integrated.
This paper demonstrates the first fully integrated BISTΣ−Δ ADC to the best of our knowledge. We propose a novel CSWF procedure and a new DSG to address the aforementioned issues of [20]. The new BIST design achieves SNDR results very close
HONG et al.: FULLY INTEGRATED BISTΣ−Δ ADC BASED ON THE MODIFIED CSWF PROCEDURE 2335
Fig. 1. Schematic of the DfDT second-orderΣ−Δ modulator [19].
to that obtained by the FFT analysis, even for the−3-dBFS 1-kHz test. In addition, the new DSG design successfully extends the BIST test bandwidth from 8 kHz to higher than 17 kHz. The new DSG also improves the SNDR results of the digital tests because the generated digital stimuli achieve higher in-band SNDRs. The rest of this paper is organized as follows: Section II describes the Σ−Δ ADC under test (AUT). Section III depicts the proposed BIST procedure and the detailed circuit implementation. This paper particularly discusses the root causes and our solutions of the limited test bandwidth and stimulus level of [20]. Section IV reveals the measurement results. Finally, Section V concludes this paper.
II. AUT
The AUT consists of two parts: 1) a second-order DfDT single-bit Σ−Δ modulator as proposed in [19] as the MUT and 2) a decimation filter. The AUT is designed for audio applications with a rated passband of 20 kHz and operates at an oversampling ratio (OSR) of 128 and a 6.144-MHz oversam-pling clock. The DfDTΣ−Δ modulator can digitally be tested with aΣ−Δ modulated bitstream. The following reviews the design.
Fig. 1 shows the schematic of the second-order DfDT single-bitΣ−Δ modulator [19]. The modulator is composed of two cascaded summing switched-capacitor (SC) integrators and a comparator, and outputs a pulse-density-modulated (PDM) bitstream DMUT, where DMUT(n) ∈ {0, 1}. Φ1 and Φ2 are two nonoverlapped clock phases derived from the oversampling clockfCLK.
A test-mode control pin T switches the operation of the DfDT modulator between the normal mode and the test mode. By settingT to 0 and fixing the digital stimulus input DBSG at 1, the switchesS1 to S5 of the first SC integrator are turned off. The DfDTΣ−Δ modulator is configured as a conventional second-order Σ−Δ modulator [22]. In the normal mode, the modulator accepts the analog stimulusVASG(z) and converts it into the PDM outputDMUT.
LetAT andXBIST(z) be the amplitude and the Z-transform of the normalized single-tone sinusoidal stimulus. The analog stimulus is expressed as
VASG(z) = ATXBIST(z). (1) Without loss of generality, aΣ−Δ modulator is usually char-acterized by its normalized I/O relationship [22]. For con-venience, YMUT≡ 2DMUT− 1 is defined as the normalized digital output of the MUT, whose value is either−1 or 1. Then, the bitstream output of the DfDT modulator in the normal mode can be described by
YMUT(z) = STFMUT(z)ATXBIST(z)
+ NTFMUT(z)EMUT(z) (2) where STFMUT(z), NTFMUT(z), and EMUT(z) represent the signal transfer function (STF), the noise transfer function (NTF), and the quantization noise of the MUT, respectively.
Let A1 andA2 be the open-loop gains of the operational amplifiers in the first and second SC integrators, respectively.
Fig. 2. In-band amplitude response and group delay of STFMUT(z) versus stimulus frequency.
The STF of the MUT is shown as [23] STFMUT(z) = α1α2z−2 1−(β1+ β2− α2)z−1+ (α1α2+ β1(β2− α2)) z−2 (3) where α1=C CS1 I1+ (CI1+ CS1+ CR1+ Cp1)A1 α2=C CS2 I2+ (CI2+ CS2+ CR2+ Cp2)A2 β1= CI1+ (CI1+ Cp1) A1 CI1+ (CI1+ CS1+ CR1+ Cp1)A1 β2= CI2+ (CI2+ Cp2) A2 CI2+ (CI2+ CS1+ CR2+ Cp2)A2. (4) Fig. 2 plots the amplitude response and the group delay of STFMUT(z) by applying the nominal design parameters of [19] to (4) and (3). For the MUT, STFMUT(z) approximately has a unit gain and a group delay of two sampling cycles within the passband. These two features will be used to simplify the BIST design in Section III.
On the other hand, the MUT operates in the test mode if the test-mode control pinT is 1. The switches SA, SB, and SE are turned off. The DfDT structure, which is highlighted by the shaded area of Fig. 1, is now reconfigured as a differential 1-bit DCC. The DCC accepts the bitstream stimulusDBSGand generates the required analog stimulus of the MUT in the test mode. The I/O relationship of the test-mode-enabled MUT is shown [19] to be
YMUT(z) = STFMUT(z)YBSG(z) + NTFMUT(z)EMUT(z). (5) A single-bit digitalΣ−Δ modulator is used to modulate the desired test stimulusATXBIST(z) and outputs the digital test stimulus YBSG for the MUT. Let STFSDM(z), NTFSDM(z),
and ESDM(z), respectively, represent the STF, the NTF, and the quantization noise of the digital Σ−Δ modulator. The normalized I/O relationship of the digitalΣ−Δ modulator is
YBSG(z)=STFSDM(z)ATXBIST(z) + NTFSDM(z)ESDM(z). (6) By (6), (5) can be rewritten as [20]
YMUT(z) = STFMUT(z)STFSDM(z)ATXBIST(z) + STFMUT(z)NTFSDM(z)ESDM(z)
+ NTFMUT(z)EMUT(z). (7)
Equations (7) and (2) indicate that the only difference be-tween the normal-mode and the test-mode outputs is the STFMUT(z)NTFSDM(z)ESDM(z) term given STFSDM(z) = 1. Since the quantization noise ESDM(z) is high-pass shaped by NTFSDM(z), the digital and the corresponding analog tests should have very similar output spectra and test results.
The single-bit characteristic of the reconfigured DCC ensures the generated analog stimuli in the test mode being purely linear. In addition, the digital test does not require a bulky antialiasing filter since the generated analog charge stimulus is already a discrete-time signal and is synchronized by the same oversampling clockfCLK.
The PDM output of the MUT is oversampled and contains significant out-of-band shaped quantization noise. The suc-cessive decimation filter removes the out-of-band noise and downsamples the output to the Nyquist rate. The decimation filter is similar to the design in [20]. The transfer function of the decimation filterHDEC(z) has an approximate unity amplitude response within the passband.
Since the decimation filter removes most out-of-passband noise in (7) and STFSDM(z) = 1 in our design, the decimated output of the test-mode-enabledΣ−Δ AUT can approximately be expressed by
YDEC(z) = STFMUT(z)HDEC(z)ATXBIST(z)
+ THDNMUT(z)HDEC(z) + OSMUT (8) where THDNMUT(z) and OSMUT are the in-band total-harmonic-distortion-plus-noise (THD+N) and the offset of the MUT, respectively. Here, we use the notation z≡
ej2πf·128/fCLKto indicate that the decimation filter’s output has
been downsampled by a factor of 128.
III. DESIGN OF THEBIST CIRCUITRY
The proposed BIST design is based on the CSWF method [21] and conducts single-tone tests. The key idea of the CSWF method is that an AUT’s output yDEC(n) can always be expressed by
yDEC(n) = yREF(n) + thdn(n) + OSMUT (9) where thdn(n), OSMUT, andyREF(n) represent the THD+N
signal, the offset, and the offset-and-THD+N-free stimulus tone response of the AUT, respectively. If we can generate a
HONG et al.: FULLY INTEGRATED BISTΣ−Δ ADC BASED ON THE MODIFIED CSWF PROCEDURE 2337
Fig. 3. Block diagram of the proposed fully integrated BISTΣ−Δ ADC.
digital reference signal identical toyREF(n), then the digitized THD+N signal can be derived in the time domain according to
thdn(n) = y
DEC(n) − OSMUT− yREF(n). (10) Calculating the power of the resulted thdn(n) signal results in the desired total THD+N power.
Fig. 3 shows the block diagram of the proposed fully inte-grated BISTΣ−Δ ADC, comprising a DSG, an ORA, and the aforementionedΣ−Δ AUT in Section II.
The DSG consists of two bitstream generators (BSGs): The stimulus BSG (SBSG) is in charge of generating the digital bitstream stimuli for the AUT, whereas the reference BSG (RBSG) generates the digital reference bitstreamyREF(n) for the BIST operation. The same stimulus frequency parameter
a21 sets the frequency of the generated stimuli, and AS and
AR set the stimulus amplitudes of the SBSG and the RBSG, respectively.
The proposed BIST design takes the advantages from three important MUT characteristics to reduce hardware overhead.
First, Fig. 2 indicates that the MUT has an approximate group delay of two oversampling clock cycles. Hence, the complex phase error calibration loop in [21] is not needed. Second, the input and output of the MUT are all single bit. Note that the bitstream output of the MUT contains similar in-band signals to the decimated output, implying that the BIST functions can be performed either before or after decimation. Therefore, this BIST design conducts the phase compensation and the subtraction for deriving the THD+N signal with the bitstream outputs of the DSG and the MUT to save hardware cost. For example, the phase compensator of this design is as simple as two cascaded flip-flops. Finally, the proposed BIST procedure further reduces the BIST hardware overhead as discussed in the following.
A. Proposed BIST Procedure
The proposed BIST procedure consists of four steps. The control signal ST EP in Fig. 3 represents the current BIST step index. Each BIST step must be a coherent test with the same stimulus frequency parameter a21. That is, a21 must be chosen such that theN decimated outputs of the AUT taken for analysis exactly contain integer cycles of the stimulus tone. The following describes the proposed BIST procedure in detail.
1) Calculating the Offset: In the beginning, a21 is loaded into the DSG. Meanwhile, AS is set to ATπ/4. The SBSG generates the bitstream stimulus ySBSG(n) for the AUT. The bitstream output of the MUTyMUT(n) flows through the multi-plexerMUXA and the decimation filter to the offset estimator. The function of the offset estimator is [20], [21]
YOS= N1 N n=1 yDEC(n). (11) By (9), (11) is rewritten as YOS= OSMUT+N1 N n=1 thdn(n) (12)
since the test is coherent, and thus, the stimulus response part of yDEC(n) vanishes after accumulation. The term (1/N)Nn=1thdn(n) in (12) approximates to zero because
thdn(n) is a random process with a zero mean. Hence, the
estimated offset YOS well approximates to OSMUT. YOS is stored in a register for the following BIST steps.
2) Calculating the Stimulus Amplitude of the Output Response: The test setup of the second BIST step is the same
as for the first step, except that the offset estimator’s output is fixed at YOS. The BIST circuitry first removesYOS from the
decimated output of the AUT. Then, the stimulus amplitude estimator accepts the offset-free responseyRES(n) through the multiplexerMUXB and estimates the stimulus amplitude of
yRES(n). This paper modifies the amplitude estimator function in [21] to be YOA2= N2 N n=1 |yA(n)| . (13) Since AS is set to ATπ/4 and the generated stimulus flows through the MUT and the decimation filter, we have
yA(n) = yRES(n) = AOsin 2πffin clkn + thdn(n) (14) where AO= π4AT|STFMUT(fin)| |HDEC(fin)| (15) and|STFMUT(fin)| and |HDEC(fin)| are the frequency ampli-tude responses of the MUT’s STF and the decimation filter at the stimulus frequencyfin, respectively. By (14), (13) can be rewritten as YOA2N2 N n=1 AOsin 2πffin clkn = 2 NAO N n=1 sin2πfin fclkn =π4AO. (16)
Consequently, the output of the amplitude estimator becomes
YOA2= AT|STFMUT(fin)| |HDEC(fin)| . (17) YOA2is stored in a register for the last BIST step.
In the similar BIST step of [20], AS is set to ATπ/2 to
simplify the ORA design. This means that the SBSG has to generate a 3.9-dB larger stimulus than needed. However, both the SBSG and the MUT are Σ−Δ modulators and will be overloaded if the stimulus amplitude exceeds their intrinsic limits [24]. As a result, the BIST results of [20] have large errors for the tests with anAT larger than−5 dBFS.
In the proposed BIST procedure, the SBSG now generates a stimulus−2.1 dB smaller than AT. Therefore, both the SBSG and the AUT are less likely to be overloaded, and the maximum
AT can be higher.
3) CalculatingAS for the Last BIST Step: The third BIST
step is an optional step for calculating the setup value ofAS in the last BIST step. In the last BIST step of [20], an additional input parameterAT|HDEC(fin)| is needed. This value depends on the decimation filter design and the test setup. In some cases, the BIST designer may not have the information.
With this additional step, the BIST designer does not need to know the detailed design of the decimation filter while the BIST results are still correct. The memory needed for storing the setup parameters of the tests is also reduced.
This BIST step setsARtoATπ/4 to generate the reference bitstreamyRBSG(n). yRBSG(n) flows through the MUXA, the decimation filter, and theMUXB to the amplitude estimator. The output of the amplitude estimator is shown to be
YOA3∼= AT|HDEC(fin)| (18) and is used to set theAS of the last BIST step.
4) Calculating the THD+N Power: The final BIST step
calculates the THD+N power. The setting values of AS and
ARare different from those in [20]. Here,ARandASare set to
YOA2andYOA3, respectively. According to (6), (7), (17), and (18), we have
YREF(z) = ATHFC(z) |STFMUT(fin)| |HDEC(fin)| × XBIST(z) + NTFSDM(z)ESDM (z) (19) YMUT(z) = STFMUT(fin)AT|HDEC(fin)| XBIST(z)
+ STFMUT(z)NTFSDM(z)ESDM(z) + NTFMUT(z)EMUT(z)
+ THDNMUT(z) + OSMUT. (20)
The term HFC(z) represents the transfer function of the phase compensator, which is z−2. By subtracting (19) from (20), the input of the decimation filter in this step is
YMUT(z) − YREF(z)
NTFSDM(z) (STFMUT(z)ESDM(z) − ESDM(z)) + NTFMUT(z)EMUT(z)
+ THDNMUT(z) + OSMUT (21)
because Fig. 2 indicates that the group delay of STFMUT(fin) is very close toz−2. The following decimation filter and the offset subtractor remove the out-of-band shaped noise and the offset. Consequently, the residue signalyRES(n) in this step only consists of the in-band THD+N signal.
Finally, the power estimator calculates the total in-band THD+N power according to PTHDN=N1 N n=1 yRES(n)2. (22)
The power estimator demands the only multiplication in the proposed BIST procedure. Because its input has been down-sampled by a factor of OSR, a simpler serial multiplier is used to implement the power estimator.
B. Design of the ORA
The major blocks of the ORA are the offset, stimulus am-plitude, and power estimators. Their functions are summarized in Table I, where N = 2048 is the number of the decimated outputs to be analyzed by the BIST circuitry for every BIST step. According to Table I, the design uses two simple ac-cumulators to realize the offset estimator and the stimulus
HONG et al.: FULLY INTEGRATED BISTΣ−Δ ADC BASED ON THE MODIFIED CSWF PROCEDURE 2339
TABLE I
FUNCTIONS OF THEORA BLOCKS
Fig. 4. Schematic of the proposed BSG with the third-orderΣ−Δ modulator.
amplitude estimator, and a serial multiplier to implement the power estimator.
An optional serial I/O interface is added to the test chip so that the BIST can conduct various tests. The serial interface can also monitor the detailed BIST results such as the estimated offset, the stimulus amplitude in the response, and the THD+N power. In practical BIST applications, this serial I/O interface is not mandatory. Instead, these outputs can be compared with some predetermined threshold values, and a single-bit pass/fail output is sufficient.
C. Design of the BSG
The BSGs must generate well-controlled and high-quality bitstream stimuli. Intuitively, the BSG can be realized by a digital oscillator cascading the aforementioned digital Σ−Δ modulator in Section II. The area-efficient oscillator circuit pro-posed in [25] is an alternative low-cost approach because it does not require any parallel multiplier. However, the BIST design that adopts the area-efficient oscillator in [25] does not show good enough BIST results [20]. The second-order digitalΣ−Δ modulator used in the oscillator is one of the root causes. For high-stimulus-frequency tests, the second-order digital Σ−Δ modulator cannot generate digital stimuli with high enough in-band SNDRs.
To enhance the SNDR of the bitstream stimulus, we propose the BSG design shown in Fig. 4. The proposed BSG is an
alternative realization of a digital resonator embedded with a third-order digital Σ−Δ modulator. The third-order digital Σ−Δ modulator plays the same role as that described by (6), which generates Σ−Δ modulated bitstreams for digital tests. According to (6), the analysis of the BSG can be divided into the stimulus and the noise parts.
For the stimulus tone part, detailed analysis shows that the loop gain of the proposed BSG is
L(z) = −a12a21(1 − zz−1STF−1)2SDM(z). (23)
To keep the oscillation stable, the Barkhausen criterion requests
L(z) = 1. Let STFSDM(z) = 1, the characteristic equation (CE) of the BSG becomes
z−2+ (a
12a21− 2)z−1+ 1 = 0. (24) Equation (24) is the same as that of [25]. Therefore, the same design criterion of [25] holds in our design as
0 < a12a21< 4 (25) fin= fCLKcos −1(1 − a 12a21/2) 2π , 0 < a12a21< 2 fin= fCLK 1 2− cos−1(1 − a 12a21/2) 2π , 2 < a12a21< 4. (26) We seta12to2−6 to simplify the circuit implementation. The desired amplitude of the generated stimulus can precisely be controlled by the initial value of Register 2 while setting the initial value of Register 1 to zero [25].
In addition to the signal part, the shaped quantization noise of the digitalΣ−Δ modulator, i.e., NTFSDM(z)ESDM(z), also circles in the oscillation loop. The shaped quantization noise may disturb the stable oscillation of the BSG. Taking the term NTFSDM(z)ESDM(z) into account, the CE of the proposed BSG is shown to be
z−2+ (a
12a21− 2)z−1+ 1
+ a12a21z−1NTFASDM(z)ESDM(z)
TXBIST(z) = 0. (27) Equation (27) must also have solutions on the unit circle of the
z-plane to generate purely sinusoidal stimuli. Since ESDM(z) is a random process, an additional criterion for the BSG design is a12a21NTFSDM(zT)ESDM(zT) ATXBIST(zT) → 0 (28)
wherezT = ej2πfin/fCLK. To generate a well-controlled stimu-lus, a12a21 and|NTFSDM(zT)ESDM(zT)| should be as small
as possible, and a larger AT is preferred according to (28). However, only the term|NTFSDM(zT)| is free for design.
Equation (28) explains why the test bandwidth of the BIST design in [20] is limited. The SNDR performance of the BSG design in [20] degrades when the stimulus frequency is
TABLE II
STRUCTURALCOEFFICIENTS OF THETHIRD-ORDER
CRFBΣ−Δ MODULATOR
high because of the necessity of a largera12a21. The shaped quantization noise power term|NTFSDM(zT)ESDM(zT)| at the
stimulus frequency is also higher. Both factors are against (28). Consequently, the generated high-frequency stimuli have poor SNDRs.
To fulfill (28) and the design criterion STFSDM(z) = 1, we adopt the cascade of resonators with distributed feedback (CRFB) structure [22] to design the third-order digitalΣ−Δ modulator shown in Fig. 4. Table II lists the structural coeffi-cients. The proposed third-orderΣ−Δ modulator has an STF exactly equal to 1, as desired. All the structure coefficients are designed to be powers of 2 to implement them without any metal–oxide–semiconductor field-effect transistor but wiring.
The proposed third-orderΣ−Δ modulator has higher order noise shaping capability and an extra zero in its NTF. Both features lower the power spectral density (PSD) of the in-band quantization noise. As a result, (28) has a superior approxima-tion to zero, although a largea21is set. That is, the BSG can sustain more stable oscillation and generates high-frequency stimuli with higher SNDRs and leads to more accurate high-frequency BIST results. The proposed BSG also improves the test accuracy of low-stimulus-level BIST results because the generated stimuli have higher SNDRs.
D. Test Setup
An important feature of the proposed BIST design is the flexibility of conducting plural tests with the same hardware. Given a single-tone test with a desired stimulus amplitudeAT and a stimulus frequency fin, the proposed BIST procedure requires only two setup parameters per test, including the stimulus frequency parametera21 and the stimulus amplitude parameterATπ/4. The setup parameters are calculated in ad-vance and stored in embedded memory or externally loaded. For the former case, the proposed BIST procedure saves the embedded memory because of the reduced number of the setup parameters. In this design, the test parameters are scanned-in through the serial I/O interface.
IV. EXPERIMENTALRESULTS
The fully integrated BISTΣ−Δ ADC has been fabricated in a 0.35-μm CMOS process. Fig. 5 shows the micrograph of the test chip. The area of the analog core is 0.66 mm2, whereas the digital functions, including the decimation filter and the BIST circuitry, occupy 2.05 mm2. Table III lists the test chip summary. The hardware overhead of the proposed BIST design
Fig. 5. Micrograph of the proposed fully integratedΣ−Δ ADC. TABLE III
SUMMARY OF THETESTCHIP
contains 13 300 digital gates, much less than the BIST design using the conventional FFT method [26]. Although the BIST area ratio seems to be high, it is because we used 0.35-μm CMOS to implement the test chip. Since all the added BIST circuits are digital, their areas will become much smaller if the BIST design is ported to an advanced process such as 0.18- or 0.13-μm CMOS. On the other hand, the MUT itself is analog, and thus, its area benefits little from the advanced process. Consequently, the area overhead ratio of the BIST design will become smaller in advanced CMOS. It is noteworthy that, since the fabrication cost per transistor is lower in advanced CMOS, the silicon cost of the additional BIST circuitry is lower as well. In the following measurements, the oversampling frequency and the OSR are 6.144 MHz and 128, respectively. The test stimulus is a −6-dBFS sinusoidal tone with a frequency of 41fclk/262 144, unless otherwise noted. The minimum-four-term window is applied to derive all spectra. Although the AUT is designed to have a 20-kHz passband, it is noteworthy that the BIST design cannot but calculate the total THD+N power within 24 kHz. Hence, the following test results are calculated using the 24-kHz THD+N bandwidth.
HONG et al.: FULLY INTEGRATED BISTΣ−Δ ADC BASED ON THE MODIFIED CSWF PROCEDURE 2341
Fig. 6. Measured in-band output spectrum of the proposed BSG with the third-order digitalΣ−Δ modulator. The BIST setup is AT= −6 dBFS and fin 1 kHz.
Fig. 7. In-band SNDRs of the proposed third-order BSG and the second-order BSG in [20].
A. Digital Stimulus Purity
Fig. 6 shows the spectrum of the generated bitstream stim-ulus by the proposed BSG. The digital stimstim-ulus achieves an in-band SNDR of 107.8 dB, which is much higher than the theoretical peak SNDR of the AUT. The zero of its NTF locates at around 15 kHz, which lowers the in-band noise floor.
Fig. 7 compares the performance of the proposed BSG with the second-order BSG in [20]. Due to better noise shaping capability, the third-order BSG provides the digital stimuli with in-band SNDR values higher than 90 dB up to 18.7 kHz. On the other hand, the SNDR values of the second-order one degrade to less than 80 dB for stimulus frequencies higher than 7.4 kHz. Since the AUT achieves a peak SNDR higher than 76 dB, the digital stimuli should have an in-band SNDR higher than 82 dB for an accurate enough peak SNDR result.
Fig. 8. Measured spectra ofyMUT(n) and yRES(n) in the fourth BIST step of the 1-kHz test.
B. BIST Results
According to the proposed BIST procedure, the decimated residue signalyRES(n) and the AUT’s decimated output should have the same THD+N spectra in the fourth BIST step. In addition, the offset and the stimulus tone power of yRES(n) should be zero. Since the current implementation cannot pro-vide the decimated AUT’s output of the fourth BIST step (an additional decimation filter is required for this purpose), we analyze the raw bitstream outputyMUT(n) instead to check the test accuracy of the BIST.
Fig. 8 shows the measured in-band spectra ofyMUT(n) and
yRES(n) in the last BIST step of the 1-kHz test. Indeed, the offset component ofyRES(n) has successfully been alleviated from−63.6 dBFS to less than −110 dBFS. The stimulus tone part ofyRES(n) is also eliminated. The residue stimulus tone power is less than−110 dBFS. In fact, the noise dominates the PSD values on the frequency bins belonging to the offset and the residue stimulus tone. Furthermore, the THD+N floors of both spectra are almost the same. The comparisons show that the THD+N information tested by the proposed BIST scheme is very similar to that by the conventional FFT analysis.
The THD+N floors have a somewhat larger difference at the frequencies close to the passband edge. It is because
yMUT(n) is not low-pass filtered by the decimation filter, whereasyRES(n) is.
Fig. 9 compares the BIST results with the corresponding FFT results at various stimulus levels to show that the proposed CSWF BIST procedure is as accurate as the conventional FFT analysis. The SNDR differences are within 0.3 to−0.7 dB. The proposed BIST design can conduct the test with a peakAT as high as −3 dBFS. However, an AT higher than −3 dBFS is not applicable since such anAT overloads the proposed third-order CRFBΣ−Δ modulator. Most high-order single-bit Σ−Δ modulators have similar limitations [27].
We also plot the test results of using the conventional analog test approach in Fig. 9 as references. The analog test results have good correlation to the digital test results and are some-what higher than the corresponding BIST test results. For low stimulus levels, the SNDR differences between analog tests
Fig. 9. Measured SNDR versus stimulus amplitude.
Fig. 10. Measured SNDR results of the proposed BIST design and the FFT analysis.
and the corresponding digital tests are less than 3 dB. The SNDR differences are higher for the stimulus levels close to the full-scale. It is noteworthy that the differences are due to the DfDT structure of the MUT, not due to the proposed BIST design [19], [24]. Since the digital stimuli areΣ−Δ modulated signals, their extra shaped noise saturates the MUT at a lower stimulus level. As a result, the digital test results with FFT and the BIST results bend down after−6 dBFS. Reference [24] proposed a decorrelating design-for-digital testability structure that can reduce the gap between the analog test results and the corresponding digital test results.
Fig. 10 compares the BIST results with their FFT counter-parts of different stimulus frequencies. The SNDR differences are less than 0.7 dB for stimulus frequencies up to 12.2 kHz and are less than 3 dB when stimulus frequencies are lower than 17 kHz. The proposed BIST design successfully extends the test bandwidth from 8 kHz [20] to over 17 kHz. Note that the FFT results have no significant degradation with respect to the stimulus frequency. The reason is that the proposed BSG
Fig. 11. Measured spectra of the decimatedyMUT(n) and yRES(n) in the fourth BIST step of the test, wherefin= 18.7 kHz.
Fig. 12. Measured BIST SNDR results, residue tone power, and the SNDR limits set by the residue tone power.
Fig. 13. Comparison of the theoretical residue tone power according to (29) with the measured data.AT = −6 dBFS.
HONG et al.: FULLY INTEGRATED BISTΣ−Δ ADC BASED ON THE MODIFIED CSWF PROCEDURE 2343
TABLE IV
PERFORMANCESUMMARY ANDCOMPARISON
provides an in-band SNDR higher than 84 dB, although the stimulus frequency is as high as 20.65 kHz.
Checking the 18.7-kHz test may help us understand why the BIST results degrade at high stimulus frequencies. In the test, the proposed BIST circuitry results in an SNDR of 65.3 dB, whereas the FFT analysis leads to an SNDR of 72.1 dB. The BIST underestimates the SNDR of the AUT by −6.8 dB. Fig. 11 shows the spectra of yMUT(n) and yRES(n) in the fourth BIST step of the test. The offset component ofyRES(n) is successfully removed, and the THD+N floors of both spectra are also very similar. However, the residue stimulus tone in
yRES(n) is as high as −72.1 dBFS. Since the residue tone itself is counted as part of the THD+N signal, it dominates the calculated THD+N power and limits the BIST SNDR result to be less than−6 − (−72.1) = 66.1 dB.
Fig. 12 shows the BIST SNDR results and the residue tone powers of different stimulus frequencies. Indeed, the worst three BIST results are limited by the too large residue tones.
The root cause of the large residue tones is the assumption used to simplify the BIST design that the group delay of the MUT is two clock cycles. Fig. 2 shows that this assumption is getting worse as the stimulus frequency increases. Letθ be the phase error in the sampling cycle. The phase error results in a residue tone whose amplitude is
2ATsin πθffin clk . (29)
Fig. 13 plots (29) and the measured residue tone power data of different stimulus frequencies whenAT = −6 dBFS.
At low frequencies, the noise floor of the AUT dominates the residue tone power. At high frequencies, the measured data follow (29) quite well. The plots show that the increasing phase
errors result in the increasing residue tones. Nevertheless, the proposed BIST design provides a test bandwidth very close to the rated signal bandwidth of the AUT. Table IV summarizes the performance of the proposed BIST design and compares with those of [13] and [20].
V. CONCLUSION
This paper has demonstrated a fully integrated BISTΣ−Δ ADC with a wide test bandwidth and high test accuracy. The new BIST procedure alleviates the possible overloading issues in [20] and reduces the number of setup parameters per test. The new BSG design with the proposed third-orderΣ−Δ modulator extends the test bandwidth by a factor of 2. Experimental results show that SNDR differences between BIST results and the corresponding FFT results are less than 3 dB within a test bandwidth of 17 kHz, which is very close to the rated passband of the AUT. The hardware overhead of the proposed BIST design only consists of 13 300 gates, making it very suitable for embedded BIST applications. The BIST design can be applied to the Σ−Δ ADCs with other DfDT structures such as the decorrelating DfDT structure [24].
ACKNOWLEDGMENT
The authors would like to thank Vanguard International Semiconductor Corporation for fabricating the test chips.
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Hao-Chiao Hong (M’04) received the B.S., M.S.,
and Ph.D. degrees from National Tsing Hua Uni-versity, Hsinchu, Taiwan, in 1990, 1992, and 2003, respectively, all in electrical engineering.
From 1997 to 2001, he was with Taiwan Semicon-ductor Manufacturing Company (TSMC), Hsinchu, where he developed mixed-signal IPs for customers and process vehicles. In August 2001, he joined the Intellectual Property Library Company, Hsinchu, as a Senior Manager of the Analog IP Department. Since February 2004, he has been with National Chiao Tung University, Hsinchu, where he is currently an Associate Professor with the Department of Electrical Engineering. He is the holder of two U.S. patents and two R.O.C. patents. His main research interests include the design-for-testability and built-in self-test techniques for mixed-signal systems and high-performance mixed-signal circuit design.
Dr. Hong is a Life Member of Taiwan IC Design Society and a member of the VLSI Test Technology Forum. He served as the Executive Secretary of the Mixed-Signal and RF (MSR) Design Consortium, Taiwan, from 2006 to 2008 and the Heterogeneous Integration (HI) Consortium, Taiwan, from 2008 to 2009.
Fang-Yi Su was born in Tainan, Taiwan, in 1982.
He received the B.S. degree in electronic engineer-ing from National Chin-Yi University, Taichung, Taiwan, in 2005 and the M.S. degree in electrical and control engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2007.
His research interests include the BIST design for mixed-signal circuits and digital IC design.
Shao-Feng Hung (S’09) received the B.S. and M.S.
degrees in electrical and control engineering in 2006 and 2009, respectively, from National Chiao Tung University, Hsinchu, Taiwan. where he is currently working toward the Ph.D. degree with the Depart-ment of Electrical Engineering.
His research interests include the DfT and BIST techniques for mixed-signal circuits and systems.
![Fig. 1. Schematic of the DfDT second-order Σ−Δ modulator [19].](https://thumb-ap.123doks.com/thumbv2/9libinfo/7631429.135183/2.891.91.783.108.555/fig-schematic-dfdt-second-order-σ-δ-modulator.webp)
