High Definition Image Pre-Processing System
for Multi-Stripe Satellites’ Image Sensors
Tsan-Jieh Chen, Student Member, IEEE, Herming Chiueh
∗, Member, IEEE, Chih-Cheng Hsieh, Member, IEEE,
Chin Yin, Wen-Hsu Chang, Hann-Huei Tsai, Member, IEEE, and Chin-Fong Chiu, Member, IEEE
Abstract— High-resolution image sensors play an important role in today’s satellites’ remote sensing applications. This paper presents an image recombination and processing system for one-dimensional multi-strip complementary metal-oxide semiconductor image sensors (CISs.) The proposed system takes advantage of the satellites’ linear moving property to control the exposure time of CIS and provides the real-time ability to generate 11 200× N high-resolution images for satellites’ remote sensing. Using hardware accelerators coupled with versatile microprocessors, the architecture is able to offer processing capability as well as long-term maintainability for space-borne platforms. The details of hardware design to meet real-time requirement are presented. The prototype, which contains four strip CISs and field programmable gate array-based prototyping, was implemented to verify functionality and capability of real-time image acquisition and combination. The implementation results show that it is feasible to integrate the proposed system into a single chip.
Index Terms— Complementary metal-oxide semiconductor (CMOS) image sensor, field programmable gate array (FPGA), microprocessor, remote sensing, space-borne platform.
I. INTRODUCTION
I
MAGE sensors play an important role in today’s satellites’ remote sensing applications, such as forest monitoring, disaster area evaluations, environment monitoring, climate monitoring, etc. Traditionally, charge-coupled devices (CCDs) are adopted in satellite’s applications. Recently, the improve-ment of CMOS image sensors (CISs) have been used inManuscript received March 29, 2012; accepted May 24, 2012. Date of publication June 11, 2012; date of current version August 1, 2012. This work was supported in part by the National Chip Implementation Center, Taiwan, the National Space Organization, Taiwan, the National Science Council, Taiwan, under Contract NSC 101-2220-E-009-017 and Contract NSC 101-2220-E-009-019, and the MoE ATU Program of National Chiao Tung University, Taiwan. The associate editor coordinating the review of this paper and approving it for publication was Dr. Subhas C. Mukhopadhyay. Asterisk
indicates corresponding author.
T.-J. Chen is with the Department of Electrical and Computer Engi-neering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]).
∗H. Chiueh is with the Department of Electrical and Computer Engi-neering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]).
C.-C. Hsieh and C. Yin are with the Department of Electrical Engi-neering, National Tsing Hua University, Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]).
W.-H. Chang, H.-H. Tsai, and C.-F. Chiu are with the National Chip Implementation Center, National Applied Research Laboratories, Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]; [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSEN.2012.2203957
. . . P h o to D io d e C e ll A D C C e ll D ig ita l C e ll 16 Cells C IS C h ip A rra y 4 ICAI Cells . . . Image Sensor Interface (ISI) SRAM ( 5.6 KB) ISI Image Combiner (IC)
SRAM Image Combiner (IC) I2C Controller Microprocessor Core 1 (MPC 1) SDRAM (64 MB) SDRAM Controller S yste m B u s MPC 2 89.6 MB/sec 22.4 MB/sec 1075 .2 MB/sec Satellite Communication Device 1433 .6 MB/sec 2867 .2 MB/sec 1433.6 MB/sec 89.6 MB/sec SRAM Controller SRAM (2 MB) H ig h D e fin itio n Im a g e P re -P ro ce ssin g S in g le C h ip 8000 lines/sec
Fig. 1. Architecture of the proposed real-time image pre-processing system for satellites’ remote sensing.
space applications [1], owing to the lower cost, lower power consumption and compatibility to nowadays well-developed CMOS integrated circuit compared to CCD’s technology. Several satellites have adopted both one-dimensional and two-dimensional CISs as their components. Satellites’ linear moving property [2], [3] to control the exposure time of line CISs provide real-time ability to generate 11,200 × N high-resolution image for satellites’ remote sensing.
Line sensor array possessing high-resolution as well as high line-rate properties imposes difficulties on CMOS semiconduc-tor fabrication. Recently, wafer-level stitching technique has been developed for high-resolution large-scale image sensors; however, it highly relied on foundries to improve yield [4]. Therefore, multiple CIS dies aligned in single package to form a high-resolution image are proposed in this study. In order to avoid the spatial discontinuity, these strip CISs are arranged in an interlaced and overlapped fashion. Thus, multi-pixel vertical gaps and horizontal overlaps are between top line sensors and bottom ones. A real-time calibration scheme is required for satellite image remote sensing.
The proposed architecture of the real-time image pre-processing system for satellites’ remote sensing is shown in Fig. 1. The system integrated sixteen strip CISs [5], four image combiner and acquisition interfaces (ICAIs) [6], an I2C controller, two microprocessors and external memories
SD Card for Imaging Evaluation P h o to D io d e C e ll A D C C e ll D ig ita l C e ll 4 Cells C IS C h ip A rra y 1 ICAI Cell Image Sensor Interface (ISI) SRAM ( 5.6 KB) Image Combiner (IC) I2C Controller MPC (Nios II) SDRAM (64 MB) SDRAM Controller S yste m B u s VGA Controller 44.8 MB/sec 11.2 MB/sec 134.4 MB/sec 179.2 MB/sec SRAM Controller SRAM (2 MB) Direct Memory Access LCD monitor for Imaging Evaluation UART Controller
T h e P ro to typ e o f H ig h D e fin itio n Im a g e P re -P ro ce ssin g S yste m
179 .2 MB/sec
4000 lines/sec
Fig. 2. Architecture of the system prototype for satellites’ remote sensing.
to build a high-resolution multiple-aspect two-dimensional images. ICAI cooperated with microprocessors are proposed to calibrate gaps and overlaps in real-time. Multiple static random access memories (SRAMs) and synchronous dynamic random access memories (SDRAMs) are utilized to improve reliability. Except for CISs and external memories, the reset of system is supposed to be integrated in a single chip because of high data bandwidth demand for image throughput. Based on the above setup, the proposed system provides the real-time capability to acquire images for the satellites’ remote sensing applications.
In this paper, a prototype of real-time image pre-processing system for satellites’ remote sensing is implemented to verify functionality and evaluate real-time performance. The archi-tecture of the prototype is shown in Fig. 2. The prototype is composed of four strip CISs, an ICAI, a custom Nios II/fast processor system [7], an SDRAM and a PC performing satellite server. The main difference between the prototype and the final system is data bandwidth demand. The final system will demand eight times larger throughput than the prototype; however, the bandwidth demand can be achieved by the proposed single chip.
The rest of this paper is organized as following. In Section II, the system architecture and performance evaluation of the prototype are described. Section III discusses hardware designs. In Section IV, implementation result is pre-sented. Following is the conclusions in this paper (Section V.)
II. ARCHITECTURE ANDPERFORMANCE
EVALUATION OF THEPROTOTYPE
The system prototype is shown in Fig. 2. In the hardware, it consists of four strip CISs, a custom Nios processor system, which is the proposed chip prototype, and personal computer (PC.) The Nios processor family [7] is 32-bit embedded-processor architecture designed specifically for the field-programmable gate array (FPGA.) The simplicity, flexibility and fixed instruction format of RISC [8] provides implementation feasibility for high processing performance.
Nios II/fast processor core is adopted in the prototype. With performance over 300 DMIPS (Dhrystones 2.1 benchmark), it is optimal for applications with large amounts of code and data. In our Nios processor system [9], [10], it implements typical bus architecture. All the transfers among peripherals (slaves) and Nios processor (master) must be passed through system bus. SRAM and SDRAM are adopted as instruction and data memory, respectively. Two additional features, video graphics array (VGA) display and secure digital (SD) card storage are applied to verify sensor performance, which will not be in the final system. To cooperate with designed hardware, functions including sensor gaps calibration and image stream out are implemented. A host computer links to the image pre-processing system via universal asynchronous receiver/transmitter (UART). In this study, the host computer plays the role of satellite control center and the image source. The satellites’ linear moving image and on-the-fly configuration are provided by a custom integrated graphic user interface (GUI) running on the host computer.
In the system prototype, only four strip CISs are adopted, which contains 2,800 pixels. The total data bandwidth of microprocessor is 400 MB/sec at 100 MHz operating rate. The front-end image bandwidth is evaluated about 11.2 MB/sec at exposure time of 250 microseconds (four sensors generate 4,000× 2,800 bytes per second, 8 bits per pixel.) Because the 8-bit pixel is required to align 32-bit data stream, 44.8 MB/sec bandwidth is consumed for bus transfer. MPC require three clock to access one pixel stream from ICAI and four clocks to access SDRAM, therefore, 134.4 MB/sec and 179.2 MB/sec is required for ICAI and SDRAM access, respectively. Therefore, a total of 313.6 MB/sec data bandwidth is required on MPC. That is feasible in 90-nm FPGA-based platform at 100 MHz clock rate; however, if sixteen strip CISs are applied in 8000 line rate, the data bandwidth demand on MPC will become a critical problem. In this study, the pre-processing architecture of line scan image sensor based on microprocessors with hardware accelerator (ICAI) is utilized. Although application-specific integrated circuit (ASIC) can provide highly processing capability and be efficient on data transfer, it is lack of flexibility. The specific hardware with a versatile microprocessor provides processing capability and flexibility. Furthermore, online configuration and programmability features of microprocessor provide long-term maintainability for space-borne application. Therefore, microprocessors-based architecture is utilized in this research. In the final system, sixteen strip CISs provide 11,200 pixels. The front-end image bandwidth as well as on-chip system bus is evaluated about 358.4 MB/sec at exposure time of 125 microseconds (sixteen sensors generate 8,000× 11,200 bytes per second.) One microprocessor does the basic pre-processing on image line by line and store results into SDRAM. The other microprocessor takes charge of block processing, such as lossless image compression, on combined image in SDRAM. The most critical bandwidth demand locates on SDRAM, which is about 2870 MB/sec. The data bandwidth can be readily achieved if the system runs at 800 MHz in nowadays chip implementation [11], [12].
704-Pixel Sensor Array T im ing D ata Pre-processing U nit (T D P)
Analog to D igital C onverter (AD C) Program m able Gain Am plifier (PGA )
C ontrol Signals from IC AI
D igital Im age Output to IC AI
I 2 CS la v e R e g is te r B an k Strip C IS C ontrol Signals from I2C C ontroller
Fig. 3. Block diagram of the strip CIS.
704-Pixel Sensor Array
Timing Data Pre-Processing Unit
PGA ADC
5 0 0 0 μ m
3150 μ
m
Fig. 4. Die photograph of the CIS for satellites’ remote sensing.
III. HARDWAREDESIGNS
In addition to the system architecture, dedicated hardware components are also key factors in real-time performance. In this section, hardware designs to meet real-time require-ments for satellites’ remote sensing are presented.
A. Satellites’ Image Sensors
The architecture of strip CIS is shown in Fig. 3. The timing data pre-processing (TDP) unit is designed to control photodiode array to store image and output data serially. Four excess photodiodes are designed for die overlapping. The analog image signal is fed into a power-efficient programmable gain amplifier (PGA) for common-mode voltage level shifting and signal amplifying. The analog output of the PGA is then digitized by a 10-bit cyclic analog-to-digital converter (ADC) [13]. All configurations of circuit blocks are stored in an I2C slave register bank. A one-shot power-on configuration is processed by the host.
The strip CIS has been fabricated with TSMC 0.18 µm triple-well CIS 1P3M technology. In order to reduce the light reflection and interference, only three metal layers were used in the whole chip. The die photograph is shown in Fig. 4.
TABLE I
SPECIFICATION OF THESATELLITES’ IMAGESENSOR
Technology TSMC 0.18 mm 1P3M
CMOS Image Sensor Process
Total Sensing Number (4 dies) 2,800
Total Sensing Number (1 die) 704
Resolution per Pixel 10 bits
Pixel Size 6.5µm × 6.5 µm
Saturation Output Voltage 1.312 V
Responsibility 3.64 V/Lux-s
Line Rate (Frame Rate) 8000 lines/s
Integration Time 125µs
Fix Pattern Noise (+2.73% / −2.7%)
(a) No overlap, 42-pixel gap 2-pixel overlap, 40-pixel gap 1-pixel overlap, 40-pixel gap (b)
Fig. 5. Photograph of four strip CISs. (a) Wire bond on PGA 370 package. (b) Different amount of vertical gaps and horizontal overlaps among sensors.
The sensor array per die has 704 pixel cells with a pixel size of 6.5× 6.5 µm2. The responsibility of sensor is 3.64 V/Lux.s; the fix pattern noise (FPN) ranged from +2.73% to −2.7%. The saturation output voltage of pixel front-end is 1.312V with 3.3V supply operation. The line rate and the required integration time are 8000 lines/s and 125 µs, respectively. The specification of the sensor is listed in Table I.
In order to evaluate the functionality, four strip CISs are bonded on PGA 370 package, which is shown in Fig. 5. The system package is fabricated by Integrated Service Technology, Inc. (website: http://www.isti.com.tw). One line is composed of 2,800 pixels (The resolution range of one line is 2,800 to 2,816 pixels depending on the assembling variation; 2,800 is the minimum guarantee value.) The interlaced place-ment is proposed to avoid the spatial discontinuity. Top strips
SR AM #2 Im age Sensor C ontrol Logic C om biner C ontrol Signals to Strip C ISs T o H ost (M icroprocessor ) 70 4 -b yt e F IFO 70 4 -b yt e St ac k 70 4 -b yt e F IFO 70 4 -b yt e St ac k M em ory #1 IC AI W R C LK R D C LK
Fig. 6. Block diagram of the proposed ICAI.
CISs are placed in reverse order and closed to bottom ones to minimize the vertical gaps. Due to the alignment variation, there are different amount of vertical gaps and horizontal overlaps among sensors, which is shown in Fig. 5(b).
The proposed ICAI consists of three blocks–Dimage sensor control logic, memory blocks and combiner. The architecture of the proposed ICAI is shown in Fig. 6. Exposure time and other sensor configurations are sent to image sensor control logic from the host. Image sensor control logic takes charge of real-time acquisition and horizontal overlaps calibration. Acquired images are stored into first-in-first-out (FIFO) mem-ory and stack, which are components in memmem-ory blocks, but overlap pixels are discarded. The last pixel is read out first without any computation in stacks so that’s the most efficient way to reverse the images from top strip CISs. The write clock, WR CLK, of FIFOs and stacks is the same rate as image sensor’s pixel rate. The read clock, RD CLK, of FIFOs and stacks is the same rate as microcontroller. Two memory blocks construct the double-buffering architecture [14]. At any one time, one memory block is actively being read out by the host, while the other block is being written acquired images from strip CISs. When drawing is complete, the roles of the two are switched with a few of switching overhead. Therefore, ICAI can continuously acquire and combine images. The processing capability of the proposed ICAI is 8,000 lines per second while operating at 32 MHz.
The space and time relationship of active pixels is illustrated in Fig. 7. Note that the reorder pixel sequence and the overlap elimination are accomplished by ICAI. The horizontal overlaps between CISK to CISK+1, are denoted as OVK, where K is
CIS index. Because CIS4 is the last sensor in the prototype, OV4 is 1. The pixel index after calibration is denoted as CK,
which can be defined as
i f(K is odd)
CK = last pi xel index in each sensor − OVK
else
CK = OVK (1)
where the last pixel index in each sensor is 704. Because OVK
1 2 3 ... 704 1 2 3 . . . 704 1 2 3 ... 704 1 2 3 . . . 704 S pac e 1 ... C1 704 ... C2 1 ... C3 704 ... C4 1. R eorder pix el s equenc e 2. C alibrate horiz ontal ov erlaps
CIS1
CIS2
CIS3
CIS4
IC A I O utput
Fig. 7. Concept of pixel sequence reorder and horizontal overlaps elimination processed by ICAI. CIS1 CIS2 CIS3 CIS4 GPK C a lib ra te ve rtica l g a p s CIS1 CIS2 CIS3 CIS4 (a) (b)
Fig. 8. Memory allocation of images. (a) Without any calibration. (b) Images are written into memory in an interleaved fashion.
Fig. 9. Setup overview of the proposed system prototype.
is known after assembling, CK can be evaluated once while
the system power on. Thus, continuous overlap elimination can be achieved.
B. Microprocessor
The microprocessor takes in charge of sensor gaps calibration and image stream out. If one line acquisition is complete, the microprocessor will be notified to read out images from ICAI. Readout of images will be written into external SDRAM in an interleaved fashion to calibrate vertical gap. The concept is shown in Fig. 8. If no calibration is applied, a straight line captured by the strip CISs will become
L in e
N(1 0 0 0 c y c le s)
< 7 8 9 cycle s T im e A cq. S tro b e C IS1O u tp u t 1 2 3 ... C IS2O u tp u t 1 2 3 ... C IS3O u tp u t 1 2 3 ... C IS4O u tp u t 1 2 3 ... 704 704 704 704 IC A I O u tp u t 1 7 0 4 C2 1 C3 7 0 4 C4 1 cycle = 2 5 0 n sL in e
N + 1 1 2 3 ... 1 2 3 ... 1 2 3 ... 1 2 3 ... 704 704 704 704 30 ns1 . C alibrate H oriz ontal O v erlap 2 . R eorder P ix el S equenc e
3 . O utput C alibration R es ults in LineN-1
μP Task 1 . C alibrate V ertic al G aps in LineN -1
2 . S tore into S D R A M 40 ns 7 0 4 C2 1 C3 C1 7 0 4 C4 1 C1
Fig. 10. Timing diagram of the implemented prototype.
(a) (b)
Fig. 11. Satellite’s image on industrial district. (a) Without any calibration. (b) Pre-processed by the chip prototype.
a stagger, which is shown in Fig. 8(a). Calibration can be done by shifting the write addresses of images with slight processing overhead, which is shown in Fig. 8(b). The start write pointer of each line image, WPtrK, can be defined as
i f(N == 1)
W PtrK = Init_W PtrK
else
W PtrK,N = W PtrK,N−1+ Comb_Pi xels (2)
where N is the N’th scanned line. The pointer is com-puted every line image access (700 pixels). The succes-sive pixels access is incremental and no computation is required. The initial memory write pointer, Init_WPtrK, can be
defined as i f(K == 1) I ni t_W PtrK = G PK× Comb_Pi xels else I ni t_W PtrK = K l=1 Pi x els− OVK− 1 +G PK× Comb_Pi xels (3)
where GPK is pixels of vertical gaps between CISK to
CISK+1. Non-overlapping pixels in each CIS are denoted as
Pixels, which ranges from 700 to 704. Combined pixels of
TABLE II
SPECIFICATION OF THEPROPOSEDIMAGEPRE-PROCESSINGSYSTEM
Total Sensing Number (16 dies) 11,200 pixels
Vertical Gaps Calibration Capability 0-64 pixels Horizontal Overlaps Calibration Capability 0-8 pixels Line Rate
(32-bit Microprocessor @ 800 MHz ICAI @ 32 MHz)
8000/second
from 2,800 to 2,816 in the prototype, and 11,200 to 11,264 in the final system. The horizontal overlaps pixels between CISK
to CISK+1, are denoted as OVK. Because Pixels, OVK, GPK,
Comb_Pixels can be obtained after assembling, Init_WPtrK
is evaluated once while the system power on; WPtrK is also
required slight computational resource. Therefore, continuous gaps calibration can be achieved by the proposed method.
IV. IMPLEMENTATIONRESULTS
The setup of the system prototype is shown in Fig. 9. Manual-focus lenses and CIS mother board was on the fixture. Lenses and CIS mother board were connected with the chip prototype via 80-wire ATA cable. The front LCD monitor showed a satellites’ linear moving image. The strip CISs captured the satellites’ image line by line and then transferred it to the chip prototype for image combination. The combination result showed on another monitor. As the system prototype powered on, initializations began and then it started continuously image acquiring and combining. In the meantime, the image quality of CIS and real-time performance of system prototype was evaluated by observing VGA display. Further image analysis, such as aspect ratio rectification [1], has been done offline on the host computer by storing image into SD card.
The timing diagram of the implemented prototype is shown in Fig. 10. The clock cycle time is 250 ns, which is 1/2000 of CIS minimum integration time. A time stage is defined as 1000 cycles, that is, 250 µs. After exposure completion, a strobe will trigger CISs to output image pixels concurrently. In the meanwhile, ICAI will acquire the image pixels by using time-division multiplexing method for horizontal overlaps calibration as well as outputting the calibrated line image in the previous time stage to the microprocessor. ICAI FIFOs and stacks readout clock is synchronous with microprocessor to meet data bandwidth demand. As long as one pixel is fetched by microprocessor, it is pushed into SDRAM for gaps calibration. Then, recurrence of fetch and push is continuous until ICAI FIFOs and stacks are empty. Gaps calibration is accomplished implicitly by SDRAM access. Every line image processing time is less than one time stage, which is 250µs. The timing diagram proves that the proposed real-time and highly-efficient processing hardware can execute continuously. The specification of the proposed system is listed in Table II. The proposed system can generate 112,00 × N in 8000 line rate while the microprocessor and ICAI run at 800 MHz and
32 MHz, respectively. 64-pixel gap and 8-pixel overlap cali-bration capability is accomplished. Gaps calicali-bration capability cannot be limited to 64 pixels; however, the more gaps need to calibrate, the more memory cells are required. In the exper-imental results, vertical gaps including misalignment error are guarantee to less than 50 pixels. Acquired and combined images are shown in Fig. 11. If no calibration was applied, dis-continuity could be seen on the image [Fig. 11(a)]. Fig. 11(b) is the real-time calibration result, which demonstrates functionality of the proposed image pre-processing system.
V. CONCLUSION
The Design and implementation of image pre-processing system were demonstrated to overcome the challenge of real-time high-resolution image acquisition and combination for satellites’ remote sensing. The proposed chip integrat-ing sixteen strip CISs, four ICAIs, and two microprocessors has been proved to be able to generate 11,200 × N high-resolution image. The prototype with four strip CISs has been implemented to verify the real-time performance of final system. Calibrated images were shown to demonstrate the functionality. The implementation result on FPGA shows the proposed system is feasible to integrate into a single chip. This research provides not only a satellites’ remote sensing platform but also a solution for high-definition line scan.
REFERENCES
[1] M. Bigasa, E. Cabrujaa, J. Forestb, and J. Salvi, “Review of CMOS image sensors,” Microelectron. J., vol. 37, no. 5, pp. 433–451, 2006. [2] J. A. Richards and X. Jia, Remote Sensing Digital Image Analysis: An
Introduction, 4th ed. New York: Springer-Verlag, 2006.
[3] J. Gao, Digital Analysis of Remotely Sensed Imagery, 1st ed. New York: McGraw-Hill, 2009.
[4] J. T. Bosiers, H. Stoldt, W. Klaassens, B. Dillen, I. Peters, E. Bogaart, R. Frost, L. Korthout, and J. Timpert, “Challenges and innovations in very-large CCD and CMOS imagers for professional imaging,” in Proc.
Silicon Photon. Integr. Circuits, Strasbourg, France, Apr. 2008, pp. 1–14.
[5] C.-C. Hsieh, W.-Y. Chen, and C.-Y. Wu, “A high performance linear current mode image sensor,” in Proc. IEEE Int. Symp. Circuits Syst., Taipei, Taiwan, May 2009, pp. 1273–1276.
[6] T.-J. Chen, H. Chiueh, H.-H. Tsai, and C.-F. Chiu, “An image combiner and acquisition interface for space remote sensing applications,” in Proc.
IEEE Int. Midwest Symp. Circuits Syst., Aug. 2009, pp. 475–478.
[7] Nios II Processor Reference Handbook. (2011) [Online]. Available: http://www.altera.com/literature/hb/nios2/n2cpu_nii5v1.pdf
[8] D. A. Patterson and D. R. Ditzel, “The case for the reduced instruction set computer,” SIGARCH Comput. Archit. News, vol. 8, no. 6, pp. 25–33, Oct. 1980.
[9] SOPC Builder User Guide. (2010) [Online]. Available: http://www.altera.com/literature/ug/ug_sopc_builder.pdf
[10] Embedded Design Handbook. (2010) [Online]. Available: http://www.altera.com/literature/hb/nios2/edh_ed_handbook.pdf [11] L. T. Clark, E. J. Hoffman, J. Miller, M. Biyani, L. Liao, S. Strazdus,
M. Morrow, K. E. Velarde, and M. A. Yarch, “An embedded 32-b microprocessor core for low-power and high-performance applications,”
IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1599–1608, Nov. 2001.
[12] A. Hasan, A. Sarangi, C. S. Baldwin, R. L. Sankman, and G. F. Taylor, “High performance package designs for a 1 GHz microprocessor,” IEEE
Trans. Adv. Packag., vol. 24, no. 4, pp. 470–476, Nov. 2001.
[13] J.-F. Lin, S.-J. Chang, C.-F. Chiu, H.-H. Tsai, and J.-J. Wang, “Low-power and wide-bandwidth cyclic ADC with capacitor and opamp reuse techniques for CMOS image sensor application,” IEEE Sensors J., vol. 9, no. 12, pp. 2044–2054, Dec. 2009.
[14] W. E. Wright, “An efficient video on-demand model,” IEEE Comput., vol. 34, no. 5, pp. 64–70, May 2001.
Tsan-Jieh Chen (S’11) received the B.S. degree in electrical engineering from the Ming Chi University of Technology, New Taipei City, Taiwan, in 2007. He is currently pursuing the Doctoral degree in electri-cal engineering at National Chiao Tung University, Hsinchu, Taiwan.
His current research interests include integrated chip design, low-power design methodology, and embedded systems for biomedical applications.
Herming Chiueh (M’90) received the B.S. degree in electrophysics from National Chiao Tung University, Hsinchu, Taiwan, and the M.S. and Ph.D. degrees in electrical engineering from the University of South-ern California, Los Angeles.
He was with Information Sciences Institute, University of Southern California, Marina del Rey, from 1996 to 2002. He has participated in the VLSI effort on several large projects in USC/ISI and most recently participated the development of a 55-million transistor processing-in-memory (PIM) chip. He is currently an Assistant Professor with the Department of Electrical and Computer Engineering, and the Deputy Director of the Biomimetic Sys-tems Research Center, National Chiao Tung University, Hsin-Chu, Taiwan. His current research interests include system-on-chip design methodology, low-power integrated circuits, neural interface circuits, and biomimetic systems.
Dr. Chiueh served as a Demonstrations Chair on the IEEE Biomedical Circuits and Systems Conferences in 2012, a Conference Secretariat on the IEEE SOC Conference in 2007, and a Finance Chair on the IEEE International Workshop on Memory Technology, Design, and Testing in 2007. He is a member of the Technical Committee on Biomedical Circuits and Systems and Nanoelectronics Gigascale Systems in the IEEE Circuits and Systems Society. He also served as the Education Affairs Officer in the IEEE Circuits and Systems Society, Taipei Chapter in 2011. He was a member of Technical Program Committee and a Session Chair in several conferences, such as ISCAS, MWSCAS, THERMINIC, APSCAS, THETA, and ICECS. From 2009 to 2012, he has given more than 12 invited talks regarding his recent research in closed-loop epileptic seizure detection and low-power sigma-delta data converters in conferences and workshops at different campuses and research institutes.
Chih-Cheng Hsieh (M’08) received the B.S., M.S., and Ph.D. degrees from the Institute of Electron-ics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, in 1990, 1991, and 1997, respec-tively.
He was with the Army of Taiwan as a Second Lieutenant from 1997 to 1999. From 1999 to 2007, he was with the IC Design House, Pixart Imaging Inc., Taiwan, and was involved in the development of CMOS image sensor ICs for PC, consumer, and mobile phone applications. He led the Mixed-Mode IC Department as a Senior Manager and helped the company to successfully become an IPO in 2007. He joined the Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, in 2007, where he is currently an Assistant Professor. He has proposed many inventions to improve the function and quality of CMOS image sensor ICs. He holds 12 U.S. patents and 23 Taiwanese patents. His current research interests include CMOS image sensor IC development for biomedical, space, robot, and customized applications, smart sensor ICs with array-level pre-processing, and low-power analog and mixed-mode IC designs.
Chin Yin received the B.S. degree from National Tsing Hua University, Hsinchu, Taiwan in 2009, where he is currently pursing the Ph.D. degree in electrical engineering.
His current research interests include analog CMOS circuits design, smart CMOS image sensors with analog pre-processing design, and Labview-based optical analysis system integration.
Wen-Hsu Chang received the B.S. and M.S. degrees in electrical engineering from the Southern Taiwan University of Technology, Tainan, Taiwan, in 2000, and 2001, respectively.
He joined the National Chip Implementation Center, Hsinchu, Taiwan, as an Assistant Researcher in 2003, where he was responsible for chip imple-mentation of environmental verification. He was promoted to a Research Associate in 2007. He joined the CMOS Image Sensor project in 2009.
Hann-Huei Tsai (M’10) received the B.S. and M.S. degrees in electrical engineering from National Cheng-Kung University, Tainan, Taiwan, in 1992 and 1994, respectively.
He was with Taiwan Semiconductor Manufac-turing Company as a Process Integration Engineer and Section Manager from 1996 to 2006. He has been with the National Chip Implementation Center, Hsinchu, Taiwan since 2006, where he is engaged in CMOS heterogeneous systems, including MEMS, BioMEMS, high-voltage and power applications.
Chin-Fong Chiu (S’92–M’95) received the B.S. degree from the Department of Electronics Engineer-ing and the Ph.D. degree from the Institute of Elec-tronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1988 and 1996, respectively.
He joined the National Chip Implementation Cen-ter, Hsinchu, Taiwan in 1993 as an Associated Researcher, working on the VLSI circuit design methodology. From 2000 to 2005, he was the Divi-sion Manager with the Chip Implementation Service Division and in charge of the promotion of RF, GaAs, and CMOS MEMS design platforms. From 2005 to 2011, he was the Deputy Director General and engaged in the development of the het-erogeneous integration and mixed-signal design platform in CMOS systems. Since 2011, he has been the Program Director for developing CMOS Imaging Sensors for space applications. His current research interests include analog integrated circuits and systems, mixed-signal circuits, and design platforms for heterogeneous integration and CIS systems.
Dr. Chiu has served as the Technical Program Committee Member and Session Chair in many conferences, such as the VLSI Design/CAD Sym-posium, VLSI-DAT, AP-ASIC, APCAS, ASPDAC, ISNE, and TESDC. He also served as a Technical Program Committee Chair on the 5th Taiwan ESD Conference, Taiwan, in 2006, and a General Chair on the 6th Tai-wan ESD Conference, TaiTai-wan, in 2007. Since 2003, he has been on the advisory committee of the Mixed-Signal and RF Consortium, Heterogeneous Integration Consortium, and Bio-Medical Electronics Consortium, Ministry of Education, Taiwan. He has served as the President of the Taiwan Electrostatic Discharge Association and a Supervisor of Nanotechnology and Micro System Association, in 2010 and 2008, respectively. He also served as a member of MEMS Committee in SEMI Taiwan, since 2010. He was the recipient of the Prof. Wen-Zen Shen Memorial Award for his outstanding contribution to the integrated circuits and system design fields from Taiwan IC Design Society in 2008. He also received the Outstanding Achievement Award in Science and Technology from the National Applied Research Laboratories in 2010.
