Effect of hot-carrier-induced interface states distribution on linear drain current degradation in 0.35 mu m n-type lateral diffused metal-oxide-semiconductor transistors

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Effect of hot-carrier-induced interface states distribution on linear drain current degradation in 0.35 ␮ m n-type lateral diffused

metal-oxide-semiconductor transistors

J. R. Lee,¹Jone F. Chen,^1,a^兲Kuo-Ming Wu,²C. M. Liu,²and S. L. Hsu²

1Institute of Microelectronics, Department of Electrical Engineering and Advanced Optoelectronic Technology Center, National Cheng Kung University, No. 1 University Road, Tainan 70101, Taiwan

2Taiwan Semiconductor Manufacturing Company, Ltd., No. 121, Park Ave. 3, Science-Based Industrial Park, Hsin-Chu 30077, Taiwan

共Received 13 December 2007; accepted 11 February 2008; published online 11 March 2008兲 The mechanisms of hot-carrier-induced linear drain current共Idlin兲 degradation in a 0.35␮m n-type lateral diffused metal-oxide-semiconductor transistor, operating at a nominal voltage of 12 V, is investigated. Results and analysis show that the location of hot-carrier-induced interface states varies with stress gate voltage. Stress-induced interface states located in accumulation region under polygate have little effect on I_dlin degradation. As a result, interface states located in drain-side spacer region dominate I_dlin degradation when interface states located in channel region are negligible. © 2008 American Institute of Physics. 关DOI:10.1063/1.2894517兴

In smart power applications, high-voltage lateral diffused metal-oxide-semiconductor 共LDMOS兲 transistors are widely used because of the compatibility to be integrated into standard low-voltage complementary MOS 共CMOS兲 process. Due to relatively high nominal operational voltage 共12⬃100 V兲, LDMOS transistors are prone to hot-carrier- induced degradation. Although hot-carrier-induced degradation of LDMOS devices has been studied,^1–8 investigation focused on the mechanism of linear drain current共Idlin兲 degradation 共increase of on resistance, Ron-sp兲 is necessary be- cause transistors with a lower R_on-sp produce smaller power consumption. In this paper, hot-carrier-induced I_dlindegrada- tion in a n-type LDMOS device is investigated. Hot-carrier stressing under a fixed drain voltage 共Vds兲 but various gate voltages 共Vgs兲 is performed. Charge pumping measurement and technology computer-aided-design共TCAD兲 simulations 共^TSUPREM4andMEDICI兲 are used to investigate the degradation mechanism. Results reveal that the location of hot- carrier-induced interface states has significant impact on I_dlin degradation.

The n-type LDMOS transistor used in this paper is fab- ricated by using a standard 0.35␮m CMOS compatible process. Figure 1共a兲 shows schematic cross section of the device. As shown in Fig.1共a兲, there are three regions between source and drain terminals, i.e., p-type channel region共Lch兲, n-type accumulation region under polygate共Lacc兲, and drain- side spacer region共Lsp兲. The gate oxide thickness of the device is 30 nm and the polygate length is 0.8␮m. Operational voltage for both V_ds and V_gs is 12 V. To accelerate hot- carrier-induced damage, stressing under V_ds= 13.2 V and various V_gs ranging from 3 to 11 V for 3000 s is performed at room temperature. I_dlinis measured under V_ds= 0.1 V and V_gs= 12 V. Threshold voltage 共Vth兲 is extracted under Vds

= 0.1 V using maximum transconductance method. During stressing, I_dlin, V_th, and charge pumping current⁹ 共ICP兲 are monitored periodically. I_CP is measured to extract stress- induced interface state density共⌬Nit兲. Figure1共b兲shows the

experimental setup of charge pumping measurement performed in this paper. The pulse in charge pumping measurement is applied to the gate while drain and bulk terminals are grounded. The source terminal is floating. The amplitude of the pulse is fixed at 10 V and base voltage 共Vbase兲 sweeps from −8 to 2 V under a frequency of 500 kHz. Rise and fall times of the pulse trains are 0.1␮s. All experiments are performed by using Agilent 4156C and an extended pulse generator.

Figure 2共a兲 shows I_dlin degradation and V_th shift as a function of stress time for devices stressed under V_ds

= 13.2 V and V_gsranging from 3 to 11 V. Results show that a higher V_gs produces more I_dlin degradation. For devices stressed under V_gs= 3 – 9 V, V_thshift is little共⬍5 mV兲, indi- cating that hot-carrier-induced damage located in L_chregion is little. Most of the damage is located in L_acc and L_sp re- gions. However, V_thshift is more than 10 mV when the de- vice is stressed under V_gs= 11 V, revealing that damage lo- cation moves into L_ch region. It has been reported that LDMOS devices exhibiting significant Kirk effect 共under high V_ds and high V_gs兲 lead to serious Idlin degradation.¹⁰ Bulk current 共Ib兲 vs Vgs characteristics under various V_ds shown in Fig.2共b兲indicate that Kirk effect is not significant in our LDMOS device because Ib does not increase at high V_gs 共Vgs= 12 V兲. Thus, the impact of Kirk effect on device degradation is not taken into consideration in our analysis.

To investigate the degradation mechanism, Fig. 3 ana- lyzes stress-induced increase in I_CP 共⌬ICP兲 for the devices shown in Fig. 2共a兲 stressed for 3000 s. Since hot-carrier- induced⌬Nitcontributes to⌬ICPwhen the gate pulse covers V_th and flat band voltage 共Vfb兲, location dependent Vth and V_fbare investigated and the results are shown in Fig. 4. V_th and V_fbare obtained from well-calibrated TCAD simulations when the carrier concentration at Si/SiO2 interface reaches 10¹⁴cm⁻³for electrons and holes, respectively. Note that V_th and V_fbdrop rapidly in L_sp region because of the weak gate control. Based on V_thand V_fbdistribution obtained in Fig.4,

⌬ICP measured at V_base= −8 V is proportional to the total

⌬Nit, i.e.,⌬Nitin L_ch, L_acc, and L_spregions because the gate pulse covers V_thand V_fbin all regions. Similarly,⌬I_CPmea-

a兲Electronic mail: jfchen@mail.ncku.edu.tw

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sured at V_base= −2 V is proportional to ⌬Nit located in L_ch and L_accregions, while⌬ICPmeasured at V_base= 0.5 V is proportional to⌬Nitlocated in L_chregion only. According to the above analysis, little ⌬ICP is observed at V_base= 0.5 V for devices stressed under V_gs= 3 – 9 V, indicating that hot- carrier-induced⌬Nitis mainly distributed in L_accand L_spre- gions. As the stress V_gsis increased to 11 V, significant⌬ICP

is observed at V_base= 0.5 V, suggesting that significant⌬Nitis created in L_chregion. Such a result is consistent with V_thshift data in Fig.2共a兲, where Vth shift is greater under V_gs= 11 V stressing. It has been reported that I_dlin degradation of con- ventional n-channel metal-oxide-semiconductor device is de- termined by total hot-carrier-induced interface states.¹¹Such an argument, however, fails to explain I_dlindegradation data when Figs.2共a兲and3are compared. Specifically, the device stressed at V_gs= 3 V has the least I_dlindegradation; however,

⌬ICPmeasured at V_base= −8 V is not the least. This indicates that not the total amount of⌬N_itbut some critical portion of

⌬Nitdominates I_dlindegradation in our LDMOS devices.

To find the critical portion of ⌬Nit that dominates I_dlin degradation, TCAD simulations are performed. The same amount of interface states distributed in a range of 0.05␮^m but centered in different locations is assigned from channel to spacer edge in simulations. I_dlindegradation resulted from interface states at different locations is shown in Fig.4. Re- sults reveal that interface states in L_sp region produce the most I_dlindegradation. Interface states in L_chregion also de- grade I_dlin but not as much as that of damage in L_sp region.

Interface states in L_accregion produce the least I_dlindegrada- tion. Such a result can be explained as follows. Under I_dlin measurement condition共Vds= 0.1 V, V_gs= 12 V兲, electrons in L_accregion are strongly accumulated such that electron concentration at Si/SiO2 interface is very high. The high electron density screens Coulomb scattering resulted from⌬Nit

in L_accregion. As a result, the effect of⌬Nitin L_accregion on I_dlindegradation becomes less effective.¹²However, electron density at Si/SiO2 interface in L_sp region is relatively less because of the weak gate control. Thus, the effect of⌬Nitin L_sp region on I_dlin degradation becomes severe. Results in Fig. 4 indicate that hot-carrier-induced ⌬Nit in L_sp region dominates device I_dlindegradation.

To confirm the above argument, hot-carrier-induced⌬Nit

located in L_spregion is extracted from⌬ICPdata as follows:¹³

⌬ICP共Vbase= − 2 −⌬V兲 − ⌬ICP共Vbase= − 2兲

= qfW冕0 x₀

⌬Nit共x兲dx, 共1兲

where x₀is a certain location in L_spregion with x = 0 defined as the drain-side polygate edge, f is the frequency of gate pulse, and W is device width. Equation 共1兲 represents the increase of⌬ICPcaused by⌬Nitdistributed from x = 0 to x₀in L_sp region. From Eq.共1兲,⌬Nitcan be extracted as follows:

⌬Nit共x兲

= − 1 qfW

⌬ICP共Vbase= − 2兲 − ⌬ICP共Vbase= − 2 −⌬V兲 dx

= − 1 qfW

d⌬Icp

dx = − 1 qfW

d⌬Icp

dV_base dV_base

dx . 共2兲

In charge pumping measurement,⌬Nitin L_spregion contributes to ⌬ICP increment when V_basesweeps below V_fb in L_sp region. Thus, the differential of V_baseis equal to the differen- tial of V_fb, i.e., dV_base/dx=dVfb/dx. From TCAD simulation result in Fig. 4, dV_fb/dx in Lsp region is roughly a constant and the value is 80.5 V/␮m. From I_CPdata, d⌬ICP/dVbaseat V_basebelow −2 V is also roughly a constant under different

FIG. 1. 共Color online兲共a兲 Schematic cross section of the n-type LDMOS device used in this paper.共b兲 The experimental setup of charge pumping measurement.

FIG. 2.共Color online兲共a兲 Idlindegradation and V_thshift as a function of stress time for devices stressed under V_ds= 13.2 V and V_gsranging from 3 to 11 V.

Higher V_gsproduces more I_dlindegradation, while V_thshift is little for devices stressed under V_gs= 3 – 9 V.共b兲 Ibvs V_gscharacteristics under various V_dsreveal that Kirk effect is not significant under high V_gs.

103510-2 Lee et al. Appl. Phys. Lett. 92, 103510共2008兲

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stressing V_gs. Thus, the average interface states density in spacer region 共⌬Nit-sp兲 can be calculated from Eq. 共2兲 as follows:

⌬Nit-sp= 1 L_spacer冕0

L_spacer

⌬Nit共x兲dx

= − 80.5 qfWL_spacer冕0

L_spacer d⌬Icp

dV_basedx

=− 80.5

qfW 冏^dV^d⌬Ibase^cp冏V_base=−8 V_base=−2

, 共3兲

where L_spaceris the length of L_spregion. Figure5 shows the relationship between device I_dlindegradation and⌬Nit-sp. For devices stressed under V_gs= 3 – 9 V, a unified relationship be- tween I_dlindegradation and⌬Nit-spis obtained. For the device stressed at V_gs= 11 V, larger I_dlindegradation is observed because⌬Nitin L_chregion also contributes to I_dlindegradation.

Results in Fig. 5 confirm that when ⌬Nit in L_ch region is negligible,⌬Nitin L_accregion is not an important factor and only⌬Nitin L_spregion dominates the I_dlin degradation.

In summary, mechanisms of hot-carrier-induced I_dlin degradation in a n-type LDMOS transistor has been pre- sented. Charge pumping measurement and TCAD simulations indicate that the device degradation is mainly caused by hot-carrier-induced ⌬Nit. For devices stressed under V_gs

= 3 – 9 V, stress-induced⌬Nitare distributed in L_acc, and L_sp regions. For the device stressed under V_gs= 11 V, ⌬Nit are distributed in L_ch, L_acc, and L_sp regions. Experimental data and TCAD simulations also reveal that⌬Nitlocated in L_acc region has little effect on I_dlindegradation, while⌬Nitlocated in L_spregion has great impact on I_dlindegradation. According to the results presented in this paper, not only the magnitude of total hot-carrier-induced⌬Nitbut also the location of⌬Nit

should be considered in evaluating the reliability of LDMOS transistors.

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FIG. 3. 共Color online兲 Stress-induced ⌬ICPas a function of V_basefor the devices shown in Fig.2共a兲stressed for 3000 s.

FIG. 4. 共Color online兲 Location dependent Vthand V_fbas well as I_dlindeg- radation resulted from⌬Nitat different locations are simulated. The drain- side polygate edge is defined as 0 in x coordinate.⌬Nitin L_spregion pro- duces the most I_dlindegradation, while⌬Nitin L_accregion produces the least I_dlindegradation.

FIG. 5. 共Color online兲 Relationship between Idlindegradation and average

⌬Nitin L_spregion is shown. A unified relationship is observed for devices stressed under V_gs= 3 – 9 V. For the device stressed at V_gs= 11 V, larger I_dlin degradation is observed because⌬Nitin L_chregion also contributes to I_dlin degradation.

103510-3 Lee et al. Appl. Phys. Lett. 92, 103510共2008兲