The Design of Switched-Capacitor Sigma-Delta Analog-to-Digital Converter 林宜宏、洪進華 ; 姚品全
E-mail: [email protected]
ABSTRACT
A high resolution sigma-delta analog-to-digital converter is proposed in this paper. To increase the performance of sigma-delta modulator in the circuit implementation, we used an operational amplifier with the cascade structure and a switched-capacitor integrator to build the second order sigma-delta modulator. The fabrication technology is TSMC 0.35μm 2P4M mixed signal process with 3.3V power supply. According to the simulation results, the estimated total power dissipation is about 20.59mW with OSR=32, SNR=56.9dB (equivalently 9-bits resolution).
Keywords : switched-capacitor ; sigma-delta modulator
Table of Contents
封面內頁 簽名頁 授權書．．．．．．．．．．．．．．．．．．．．．．．．．iii 中文摘要．．．．．．．．．．．．
．．．．．．．．．．．．iv 英文摘要．．．．．．．．．．．．．．．．．．．．．．．． v 誌謝．．．．．．．．．
．．．．．．．．．．．．．．．．．vi 目錄．．．．．．．．．．．．．．．．．．．．．．．．．．vii 圖目錄．．．
．．．．．．．．．．．．．．．．．．．．．． x 表目錄．．．．．．．．．．．．．．．．．．．．．．．．．xiii 第一章 緒論 1.1 研究動機 ．．．．．．．．．．．．．．．．．．1 1.2 類比數位與數位類比轉換器 ．．．．．．．．
．．2 1.2.1 類比數位轉換器．．．．．．．．．．．．．2 1.2.2 數位類比轉換器．．．．．．．．．．．．．3 1.3 奈奎氏 率與超取樣類比數位轉換器 ．．．．．．．4 1.3.1 奈奎氏率類比數位轉換器．．．．．．．．．5 1.3.2 超取樣類比數位轉 換器．．．．．．．．．．6 1.4 論文章節架構 ．．．．．．．．．．．．．．．．8 第二章 和差類比數位轉換器原理架 構 2.1 奈奎氏率與量化誤差 ．．．．．．．．．．．．．9 2.1.1 脈波調變技術．．．．．．．．．．．．．．9 2.1.2 奈奎 氏率 ．．．．．．．．．．．．．．．10 2.1.3 量化誤差 ．．．．．．．．．．．．．．．11 2.2 和差類比數位轉換器技 術．．．．．．．．．．．13 2.2.1 超取樣技術 ．．．．．．．．．．．．．．14 2.2.2 雜訊移頻技術 ．．．．．．．．
．．．．．16 2.3 和差類比數位轉換器．．．．．．．．．．．．．17 2.3.1 一階和差類比數位轉換器 ．．．．．．．
．18 2.3.2 二階和差類比數位轉換器 ．．．．．．．．22 2.4 數位降頻濾波器．．．．．．．．．．．．．．．25 第三章 交換式電容電路 3.1 交換式電容電路原理．．．．．．．．．．．．．26 3.2 交換式電容電路基本元件．．．．．．．
．．．．28 3.2.1 MOS開關．．．．．．．．．．．．．．．29 3.2.2 非重疊時脈 ．．．．．．．．．．．．．．32 3.3 交換式電容積分器原理．．．．．．．．．．．．33 3.3.1 敏感性積分器 ．．．．．．．．．．．．．33 3.3.2 非敏感性積 分器 ．．．．．．．．．．．．36 3.3.3 信號流程圖分析 ．．．．．．．．．．．．40 3.4 交換式電流電路．．．．．．
．．．．．．．．．42 3.5 交換式電容電路與交換式電流電路比較．．．．．44 第四章 電路設計與模擬分析 4.1 和差調 變技術．．．．．．．．．．．．．．．．48 4.2 和差類比數位轉換器實現．．．．．．．．．．．51 4.2.1 類比開關 ．
．．．．．．．．．．．．．．52 4.2.2 運算放大器 ．．．．．．．．．．．．．．53 4.2.3 積分器 ．．．．．．．．．
．．．．．．．55 4.2.4 一位元數位類比轉換器 ．．．．．．．．．56 4.2.5 非重疊時脈產生器電路 ．．．．．．．．
．57 4.2.6 一階和差類比數位轉換器 ．．．．．．．．59 4.2.7 二階和差類比數位轉換器 ．．．．．．．．62 4.2.8 實體層 佈局考量 ．．．．．．．．．．．．65 第五章 結論 5.1 結論．．．．．．．．．．．．．．．．．．．．68 5.2 未來方 向．．．．．．．．．．．．．．．．．．69 參考文獻．．．．．．．．．．．．．．．．．．．．．．．．70
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