The Design and Analysis of Dual-Delay-Path Ring Oscillators
Zuow-Zun Chen and Tai-Cheng Lee, Member, IEEE
Abstract—A dual-operation-mode ring oscillator that employs dual-delay paths is presented. The two operation modes, referred to as the differential and common modes, have different output waveform characteristics and oscillation frequencies. A nonlinear model for the dual-delay-path ring oscillator and the analysis of the stability of each operation mode are proposed to confirm both simulation and measurement results. Furthermore, a method for operation-mode selection is presented. The differential four-stage dual-delay-path ring oscillator is fabricated in a 0.18- m CMOS technology. Measurements show that the tuning ranges are from 1.77 to 1.92 GHz and from 1.01 to 1.055 GHz for differential- and common-mode operations, respectively.
Index Terms—Multiphase signals, phase-locked loops (PLLs), ring oscillators, voltage-control oscillators.
I. INTRODUCTION
R
ING OSCILLATORS have been widely employed in most clock generators and frequency synthesizers for their small die size, quadrature or multiphase outputs, and easy integration in standard CMOS technologies. Because the oscil- lation frequency of ring oscillators is mainly determined by the propagation delay of each delay cell, the maximum frequency of single-loop ring oscillators is limited by the delay time of the delay cells. Several techniques have been reported to explore the maximum frequency levels of ring oscillators [1]–[9]. These topologies are similar in that auxiliary delay paths are used to construct fast subfeedback loops. Although ring oscillators with auxiliary delay paths exhibit higher oscillation frequencies, it is found that they may have more than one stable operation mode.Multiple operation modes in such type of ring oscillators were also pointed out in [5] and [8]; however, the characteristics of the multiple operation modes, such as the number of operation modes, oscillation frequencies, amplitudes, and phase relation between each stage, are limited. Thus, it is risky for a system to rely on such ring oscillators. For example, in phase-locked loops (PLLs), the behavior of the voltage-controlled oscillator should be well determined; otherwise, the PLLs may fail to lock the input clock.
Multiple operation modes of various types of -tank oscil- lators have been investigated in the past. Two stable operation
Manuscript received January 14, 2010; revised May 12, 2010; accepted July 07, 2010. Date of publication November 15, 2010; date of current version Feb- ruary 24, 2011. This work was supported by National Science Council (NSC) under Contract 98-2220-E-002-035- and 98-2622-8-002-001-A1. This paper was recommended by Associate Editor A. Tasic.
The authors are with the Department of Electrical Engineering and the Grad- uate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan.
Color versions of one or more of the figures in this paper are available online
Fig. 1. Differential four-stage dual-delay-path ring oscillator.
modes were reported for a fourth-order -tank oscillator [10], [11]. The multiple operation modes of coupled -tank oscil- lators were studied in [12] and [13]. It was shown that, because of circuit nonlinearity, the operational mode with the greatest gain or the one that is properly initiated sustains, whereas the other modes die off. Recently, the ambiguous multiple operation modes of quadrature oscillators and injection-locked oscil- lators were interpreted using a hard-limiting nonlinear model and perturbation method [14], [15].
Multiple operation modes of ring oscillators with auxiliary delay paths are, compared with -tank oscillators, less re- ported. In this work, a differential four-stage dual-delay-path ring oscillator is implemented for its high oscillation frequen- cies, as shown in Fig. 1[6]. Experimental results indicate that the ring oscillator has two stable operation modes. When turning the power on and off, the oscillator is found operating in either a mode with the designed oscillation frequency or a mode with almost half of the designed oscillation frequency. The two op- eration modes are discriminated by their oscillation frequencies and output waveform characteristics. In contrast to the typical differential outputs of a single delay cell, the outputs are in phase in the other operation mode. Moreover, the output amplitudes of the two modes are different. The main objective of this study is to resolve the ambiguous dual operation modes in differen- tial four-stage dual-delay-path ring oscillators and provide de- sign strategies for similar types of ring oscillators. To this end, we use a small-signal linear model to predict possible operation modes of the ring oscillator. Thereafter, the stability of the two modes is shown by introducing a nonlinear model of the ring oscillator where differential pairs are modeled as hard-limiting transconductors. The stability of either mode manifests the req- uisite considerations for operation-mode selection. The linear and nonlinear models provide full insight into the fundamental behaviors of the dual-operation-mode ring oscillator.
The rest of this paper is organized as follows. In Section II, the two operation modes of a differential four-stage dual-delay-path ring oscillator are predicted in a theoretical small-signal linear
mode. The circuit technique for operation-mode selection is pro- posed in Section IV. In Section V, experimental results of a differential four-stage dual-delay-path ring oscillator are pre- sented. Finally, the paper is concluded in Section VI.
II. SMALL-SIGNALLINEARMODEL
Fig. 2 shows the schematic of a delay cell in the ring os- cillator shown in Fig. 1. Because the long propagation delay in single-loop ring oscillators limits the oscillation frequency, delay cells with an auxiliary delay path is introduced to re- duce the delay time and improve the oscillation frequency [6].
Transistors and are the input devices of the main delay signal and the auxiliary delay signal, respectively.
constitutes a CMOS latch whose driving strength is controlled by . Specifically, when is high, the ef- fective driving strength of the latch becomes strong and it re- sists the voltage switching in the differential delay cell. Conse- quently, the delay time increases. To illustrate the possible oper- ation modes of the ring oscillator, a simplified model is first pre- sented. Fig. 3(a) and (b) shows the redrawn circuit schematics of the ring oscillator in Fig. 1. Each node is denoted with respect to Fig. 1. The inverters in Fig. 3(b) represent the equivalent circuit in gate level. and are the simplified loading capacitance and equivalent resistance at the output node, respectively. For simplicity, the transistors used for frequency tuning in Fig. 2 are neglected in this model. The simplified model makes the analysis easier while maintaining the essence of the oscil- lator. According to Fig. 3, the vector differential equation de- scribing the node voltages of the ring oscillator can be written as
(1) where
(2)
(3) Vectors , , and denote the output currents of inverter stages , , and , respectively; , , and are their output current functions. It should be noted that dc components are not included in the
voltage and current expressions of (2) and (3). Since these functions are intrinsically nonlinear, the analysis performed on the basis of these nonlinear functions is typically complicated.
However, a first-order linear function describing small-signal behavior at the bias point can be derived. For square-law MOSFET transistors
(4)
and are the corresponding dc current and transcon- ductance of the active devices at the bias point, respectively,
where is , , or and is , , , , , , , or
. Equation (3) can then be rewritten as
(5) Substituting (5) into (1), a system of first-order linear equations can be obtained, , where is an 8 8 matrix defined as shown at the bottom of the page. , , and are the products of , , and with , respec- tively. Fig. 4(a) shows a plot of the eight eigenvalues of matrix on the complex plane. Parameters are evaluated by a SPICE simulation at the bias point, and is normalized to unity. In this case, no auxiliary delay path is involved . Only one pair of eigenvalues lies in the right half plane, and their values are
(7) For this complex pair of eigenvalues, the general solution of (1) can be postulated as
... (8)
(6)
Fig. 2. Circuit implementation of delay cell.
Fig. 3. (a) Simplified model of differential four-stage dual-delay-path ring os- cillator. (b) Circuit of delay stages in (a).
where is a constant. In practice, the gain term is made greater than zero, so that periodic oscillation with an angular frequency given by will grow exponentially. As the am- plitude increases, the oscillator departs from linearity and non- linear terms should be considered. The amplitude will be even- tually limited, and the oscillator remains in steady-state oscilla- tion. Fig. 4(b) shows the phase relation of each output node.
If the auxiliary path is added, rises from zero and leads to an increment in the frequency term , as indicated in (7).
Thus, a higher oscillation frequency can be attained. However, by increasing , the real part of another pair of eigenvalues tends to increase. This pair is given by
(9) The general solution of (1) for this pair of eigenvalues is
Fig. 4. (a) Eigenvalues of . (b) Phasor diagram of general solution .
where is a constant. When increases, moves to
the right. As exceeds , enters the right
half plane, as shown in Fig. 5(a). The phase relation of each output node in this case is shown in Fig. 5(b). Now, in addition to the original pair of eigenvalues, another pair is located in the right half plane. When the oscillator starts up, initially, the signals and are small and the linear model is valid. By the superposition principle, the output node signal can be expressed as
(11) If and are both positive, the amplitudes of the two op- eration modes increase. Since the other eigenvalues lie in the left half plane, their respective signals lead to decaying exponential terms and can be ignored. The analysis, thus far, neglects nonlin- earities of the oscillator. This may imply that the ring oscillator can oscillate in the two operation modes simultaneously. How- ever, as the amplitude grows up, nonlinearity of the oscillator circuit would take place, one of the operation modes dominates the ring oscillator and the other dies away. The mechanism that drives operation-mode selection will be discussed later.
III. NONLINEARANALYSIS OFDUAL-OPERATION-MODERING
OSCILLATORS
In Section II, a small-signal linear approach was presented for predicting the two operation modes of a differential four-stage dual-delay-path ring oscillator. In general, the nonlinear cur- rent functions , , and are rather compli- cated. Several attempts characterized by polynomials have been made to approximate the functions [10]–[13]. Nevertheless, a rather straightforward method is to model differential circuits as hard-limiting transconductors [14], [15], as shown in Fig. 6(a).
Fig. 5. (a) Eigenvalues of . (b) Phasor diagram of general solution .
voltage, although the hard limiter produces a square-wave cur- rent, only the fundamental of the output current is concerned.
The circuit shown in Fig. 6(b) can be expressed by the differen- tial equation
(12) We assume the input and output voltages are sinusoidal
signals , ,
and . The hard limiters are driven
by the sinusoidal voltages and produce square-wave cur-
rents with fundamentals of and
, where and denote the
equivalent tail currents. By substituting the terms into (12) and separating the real and imaginary parts, the time-varying phase and amplitude of the output node are obtained as
(13) Assume that the oscillator starts up from the bias point and the dc gains of differential and common modes do not vary with
Fig. 6. (a) Differential pair circuit modeled as hard-limiting transconductors.
(b) Operation of hard-limiting transconductors.
time. The amplitude of the signal with larger gain rises faster.
In fact, referring to (8) and (10), the signal with larger gain term value contains an exponential part that grows faster. More- over, although multiple operation modes are possible, since the signal with larger amplitude drives the clipping characteristic of the hard limiter, the smaller signals will be suppressed [14].
In other words, the larger signal dominates the nonlinear circuit and the gain of the lagging operation mode is reduced. The lag- ging operation mode dies off, and the dominating mode reaches steady-state oscillation. In what follows, the stability of the two possible operation modes of the ring oscillator is analyzed by properly applying the nonlinear model in each case.
A. Differential-Mode Operation
For the first operation mode derived in (8) and shown in Fig. 4(b), the output waveforms and are differentially phased, as are and , and , and and . Thus, operation in this mode is referred to as differential-mode oper- ation. Considering the differential phase characteristic of these signals, the circuit diagram of Fig. 3 is redrawn by substituting the differential pairs with the hard-limiting model shown in Fig. 6(a). The rearranged diagram is shown in Fig. 7. The process is similar to representing differential pairs with their half-circuit equivalents. By applying (12) and (13) to each stage and as previously defined, equals to half the tail current of a differential pair. The state equations for the ring oscillator are obtained as shown at the bottom of the next page. In steady state, the amplitudes of output signals remain constant and
...
(14)
the derivatives of phases are constants equal to the oscillation frequency . The steady-state output amplitude and oscillation frequency can be derived from (14) as
(15)
where . To
investigate the stability of differential-mode operation, we con- sider the effect of a small disturbance and investigate the prop- erties of (14) in response to this disturbance. Small fluctuations in the phases at a fixed point are introduced as
(16) Substituting (16) into (14) and assuming that the amplitude varies slowly, we obtain the differential equations
(17)
where and
(18) The eigenvalues of the matrix on the right-hand side of (17) are
(19) Fig. 8 shows that all eigenvalues lie in the left half plane, ex- cept for the eigenvalue at the origin, where is normalized to unity. This proves the stability of differential-mode operation.
The zero eigenvalue exhibits the integration property of ring os- cillators with small phase disturbance. As mentioned in [15], this indicates that the free-running oscillator is an autonomous phase integrator.
B. Common-Mode Operation
Fig. 7. (a) Nonlinear model of the ring oscillator operating in differential mode.
(b) Circuit of delay stages in (a).
Fig. 8. Locations of eigenvalues.
and . Thus, this operation mode is referred to as common- mode operation, in contrary to the differential-mode operation which has differential output characteristics. Additionally, and are differentially phased, as are and . We redraw the full circuit diagram of Fig. 3 by substituting the differential pairs with the hard-limiting model in Fig. 6(a). The simplified schematic is shown in Fig. 9. Now, applying (12) and (13) to each stage, we obtain the state equations
(20) The steady-state output amplitude and oscillation frequency in common-mode operation are given as
Fig. 9. Nonlinear model of the ring oscillator operating in common mode.
Fig. 10. Output waveforms. (a) Differential-mode operation. (b) Common- mode operation.
where . We
now perturb the phases at the fixed point, i.e.,
(22) Substituting (22) into (20) and assuming that the amplitude varies slowly results in the following differential equations:
for (23)
The eigenvalues of matrix are 2 and 0, which shows the stability of common-mode operation.
Fig. 10(a) and (b) shows the output waveforms of the differ- ential four-stage dual-delay-path ring oscillator operating in the differential and common modes, respectively. As predicted by the small-signal linear model, the outputs and are differ- entially phased in differential-mode operation and are in phase
in common-mode operation. Moreover, the steady-state ampli- tude and oscillation frequency are different in the two operation modes, as indicated in (15) and (21).
IV. OPERATION-MODESELECTION
The proposed nonlinear analysis shows that the ring oscillator remains stable in each mode. Therefore, it is important to ensure that the ring oscillator starts up in the mode of interest (typically the differential mode). As mentioned previously, when the ring oscillator starts up from its bias point and if dc gains do not vary with time, the signal that grows fastest suppresses the others at the output [14]. With this property, (7) and (9) can be used for design considerations. When the oscillation begins, initially, the two signals are small; if is greater than , the differen- tial-mode amplitude grows faster and dominates the nonlinear circuit. That is
(24)
Ratio value is introduced for expression convenience. To achieve high-frequency oscillation, is chosen to be relatively small and can be neglected in the mode-selection design consideration. Therefore, (24) becomes
or
(25)
If the oscillation starts from the bias point where
(latch device ignored), the constraint to ensure dif-
ferential-mode operation is .
However, the rate at which the power supply ramps up from 0 to 1.8 V also affects mode selection. It has been found for the delay cell shown in Fig. 2 that, even if the dc differential-mode gain is designed larger than common-mode gain at the bias point, differential-mode gain may be smaller than common-mode gain during power-supply ramp-up, as explained below. During ramping up of the power supply, the ring oscillator has iden- tical output node voltage before the oscillation begins. Thus, the circuit can be considered as diode-connected transistors, as shown in Fig. 11(a). Current flows through the output loadings and charges . Here, is the sum of drain currents
, , and . Because is greater than
during ramping up of the power supply, the value in (25) becomes less than unity for a period of time, which implies common-mode gain greater than differential-mode gain. Fig. 11(b) shows the value in (25) with respect to time in a SPICE simulation under 1- s power-supply ramp-up rate.
As shown, during power-supply ramp-up, is less than unity in region A, and as the power supply continues to rise, becomes larger than unity in region B. This causes uncertain steady-state operation mode; either differential or common mode sustains.
Fig. 12(a) and (b) shows the output waveforms under fast and slow power-supply ramp-up rate; the ring oscillator operates in differential and common modes, respectively. The results of a
Fig. 11. (a) Equivalent circuit. (b) Simulated gain ratio.
more elaborated simulation are shown in Fig. 13, where dif- ferent power-supply ramp-up rates and various gain term values were tested by sweeping the multiplier number of aux- iliary devices. Simulation shows that, after power supply set- tles down, the ring oscillator operates in either differential or common mode. Neither simultaneous oscillation of differential and common mode nor other operation modes have been ob- served. Furthermore, as indicated in the figure, larger and longer power-supply ramp-up time, which causes longer pe- riod of time for greater than (region A), gives the common-mode amplitude more time to build up and dominate the nonlinear circuit. In contrast, shorter power-supply ramp-up time and smaller drives the steady-state operation of the ring oscillator to differential mode. Therefore, for mode selec- tion, the gain ratio during power-supply ramp-up needs to be considered as well. should be designed greater than throughout the entire ramp-up process. However, this gives rise to design tradeoffs between high-frequency oscillation and gain values [8]. For example, designing the dual-delay-path ring os- cillator with weaker auxiliary devices or stronger latch devices decreases common-mode gain, but also reduces the oscillation frequency of differential mode.
To eliminate the dependence of gain ratio with respect to power-supply ramp-up rate, which causes ambiguous steady-state operation, and to ensure differential-mode (or common-mode) operation, a startup circuit is presented, as shown in Fig. 14(a). The circuit is composed of eight identical subblocks, and the output of each subblock is connected to one of the output nodes of the ring oscillator. The startup circuit charges the output nodes to a predefined initial value at circuit startup. The operation is shown in Fig. 14(a). When
Fig. 12. Operation-mode simulation. (a) Fast power-supply ramp-up. (b) Slow power-supply ramp-up.
Fig. 13. Operation-mode simulation of different multiplier numbers of auxil- iary devices and different rates of power-supply ramp-up from 0 to 1.8 V.
initial condition value. The startup circuit was tested through simulations under various gain term values by sweeping the multiplier number of auxiliary devices. Fig. 14(b) shows the simulation results. Since the startup circuit is employed, the power-supply ramp-up rate does not need to be considered.
The black line shows the case that output nodes are precharged to ensure differential-mode operation; the gray line shows the case of output nodes precharged to ensure common-mode oper- ation. Simulation results show that the startup circuit correctly controls the oscillator to operate in either mode. In Fig. 14(b) and as derived in (15) and (21), a larger increases the oscillation frequency of differential mode and decreases
Fig. 14. (a) Startup circuit. (b) Simulated oscillation frequency of ring oscil- lator with startup circuit employed.
Fig. 15. (a) Microphotograph of the dual-delay-path ring oscillator. (b) Mea- surement setup.
becomes large and eventually cancels out the driving strength of the increment and reduces the frequency.
V. EXPERIMENTALRESULTS
A differential four-stage dual-delay-path ring oscillator was designed and fabricated in 0.18- m CMOS technology.
Fig. 15(a) shows the microphotograph of the fabricated circuit.
To achieve high-frequency oscillation in differential mode, the auxiliary devices are designed to be stronger and latch devices designed to be weaker. The two operation
Fig. 16. Measured output waveform. (a) Output waveform. (b) Zoom in.
Fig. 17. Output spectrum and frequency range of the ring oscillator. (a) Differ- ential mode. (b) Common mode.
modes are experimentally demonstrated. It should be noted that the fabricated dual-delay-path ring oscillator contains no startup circuit, because the dual-mode operation was found during the experiment rather than in the design and simulation stage. To specify either operation mode for measurement, a different ramp-up rate of the power supply is applied to start up oscillation, as already verified by the SPICE simulations shown in Figs. 12 and 13. The measurement setup is shown in Fig. 15(b). To control the power startup, an arbitrary waveform generator (Tektronix AWG520) is used to supply voltage to the ring oscillator. A sequential power-supply signal with a slow ramp-up slope followed by a steep ramp-up slope is applied to
TABLE I
SUMMARY OFEXPERIMENTALRESULTS
the ring oscillator, as shown in the lower portion of Fig. 15(b).
The output waveforms measured using an oscilloscope (Agilent DSO80404B) are shown in Fig. 16. In Fig. 16(b), the oscillation frequency with the slow ramp-up of the power supply is about half of that with the fast ramp-up, indicating the operation of the ring oscillator in the differential and common mode, respec- tively. This is in agreement with postsimulation results. The output tuning characteristics were measured using a spectrum analyzer (Agilent E4404B). The supply voltage was set to 1.8 V after properly starting up the ring oscillator. Fig. 17(a) and (b) shows the output spectrum and frequency range of the ring oscillator operating in the differential and common modes, respectively. Table I summarizes the experimental results.
VI. CONCLUSION
Ring oscillators with auxiliary delay paths are often em- ployed for obtaining higher oscillation frequencies in ring oscillators. However, multiple operation modes are found in such type of ring oscillators. A differential four-stage dual-delay-path ring oscillator that generates dual-operation mode has been presented. The main difference between the two operation modes is the output waveform characteristic. Instead of typical differential outputs in a single delay cell, the outputs are in phase in the other mode. Moreover, the amplitude and oscillation frequency of the two modes differ. In this paper, a small-signal linear model has been proposed for predicting the two operation modes of differential four-stage dual-delay-path ring oscillators. In nonlinear model analysis, the two opera- tion modes are shown to provide steady-state oscillation. The analysis based on linear and nonlinear models shows the fun- damental behaviors of the two operation modes and provides design guidelines for dual-delay-path ring oscillators. Proper initialization of the oscillator is required. A startup circuit has been proposed to control the operation modes.
REFERENCES
[1] D. Y. Jeong, S. H. Chai, W. C. Song, and G. H. Cho, “CMOS current- controlled oscillators using multiple-feedback-loop architectures,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 1997, pp. 386–387.
[2] S. J. Lee, B. Kim, and K. Lee, “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme,”
IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 289–291, Feb. 1997.
[3] C. H. Park and B. Kim, “A low-noise, 900-MHz VCO in 0.6- m CMOS,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 586–591, May 1999.
[4] L. Sun, T. Kwasniewski, and K. Iniewski, “A quadrature output voltage controlled ring oscillator based on three-stage subfeedback loops,” in Proc. IEEE ISCAS, Jul. 1999, vol. 2, pp. 176–179.
[5] L. Sun and T. A. Kwasniewski, “A 1.25-GHz 0.35- m monolithic CMOS PLL based on a multiphase ring oscillator,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 910–916, Jun. 2001.
[6] Y. A. Eken and J. P. Uyemura, “A 5.9-GHz voltage-controlled ring oscillator in 0.18- m CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 230–333, Jan. 2004.
[7] Y. A. Eken and J. P. Uyemura, “The design of a 14 GHz I/Q ring os- cillator in 0.18 m CMOS,” in Proc. IEEE ISCAS, May 2004, vol. 4, pp. 133–136.
[8] S. S. Mohan, W. S. Chan, D. M. Colleran, S. F. Greenwood, J. E.
Gamble, and I. G. Kouznetsov, “Differential ring oscillators with mul- tipath delay stages,” in Proc. IEEE CICC, Sep. 2005, pp. 503–506.
[9] C.-Y. Yang, C.-H. Chang, and W.-G. Wong, “A PLL-based spread-spectrum clock generator with a ditherless fractional topology,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 1, pp. 51–59, Jan. 2009.
[10] B. van der Pol, “On oscillation hysteresis in a triode generator with two degrees of freedom,” Philos. Mag., vol. 43, no. 256, pp. 700–719, Apr.
1922.
[11] A. Goel and H. Hashemi, “Frequency switching in dual-resonance os- cillators,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 571–582, Mar. 2007.
[12] T. Endo and S. Mori, “Mode analysis of a multimode ladder oscillator,”
IEEE Trans. Circuits Syst., vol. CAS-23, no. 2, pp. 100–113, Feb. 1976.
[13] T. Endo and S. Mori, “Mode analysis of a ring of a large number of mutually coupled van der pol oscillators,” IEEE Trans. Circuits Syst., vol. CAS-25, no. 1, pp. 7–18, Jan. 1976.
[14] A. Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, and A. A. Abidi,
“The quadrature LC oscillator: A complete portrait based on injection locking,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1916–1932, Sep. 2007.
[15] A. Mirzaei, M. E. Heidari, R. Bagheri, and A. A. Abidi, “Multi-phase injection widens lock range of ring-oscillator-based frequency di- viders,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 656–671, Mar.
2008.
Zuow-Zun Chen was born in Taipei, Taiwan, in 1982. He received the B.S. degree in computer science and information engineering and the M.S.
degree in electrical engineering from National Taiwan University, Taipei, in 2005 and 2008, respec- tively.
He is currently with the Graduate Institute of Electronics Engineering, National Taiwan Univer- sity. His research interests are analog phase-locked loops, frequency synthesizers, ring oscillators, and mixed-mode circuits.
Tai-Cheng Lee was born in Taiwan in 1970. He re- ceived the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1992, the M.S. degree in electrical engineering from Stan- ford University, Stanford, CA, in 1994, and the Ph.D.
degree in electrical engineering from the University of California, Los Angeles, in 2001.
He was with LSI Logic from 1994 to 1997 as a Circuit Design Engineer. He was an Adjunct Assis- tant Professor with the Graduate Institute of Elec- tronics Engineering (GIEE), National Taiwan Uni- versity, from 2001 to 2002. Since 2002, he has been with the Department of Electrical Engineering and GIEE, National Taiwan University, where he is a Professor. His main research interests are in high-speed mixed-signal and analog circuit design, data converters, phase-locked-loop systems, and RF circuits.
