A New FPGA Implementation for Four Switch Three Phase Inverter

A New FPGA Implementation Of Four- Switch Three- Phase Inverter

Phan Quoc Dzung

Faculty of Electrical &

Electronic Engineering HCMC University of

Technology Ho Chi Minh City,

Vietnam pqdung@hcmut.edu.vn

Le Minh Phuong

Faculty of Electrical &

Electronic Engineering HCMC University of

Technology Ho Chi Minh City,

Vietnam lmphuong@hcmut.edu.vn

Hong Hee Lee

NARC, Ulsan University, Korea hhlee@mail.ulsan.ac.kr

Bui Ngoc Thang

HCMC University of Technology Ho Chi Minh City,

Vietnam buingocthang1984@yahoo.

com

Le Dinh Khoa

Faculty of Electrical &

Electronic Engineering HCMC University of

Technology Ho Chi Minh City,

Vietnam

khoaledinh@hcmut.edu.vn

Abstract -- This paper is concerned on FPGA design for control implementations of four switch three phase inverters (B4, FSTPI). This paper is to present a space vector PWM algorithm for four switch three phase inverters (B4, FSTPI) based on the one for six switch three phase inverters (B6, SSTPI) (principle of similarity) where the αβ plan is divided into 6 sectors and the formation of the required reference voltage space vector is done in the same way as for B6 by using effective (mean) vectors. An SVPWM technique has been developed using the ready-to-use field-programmable gate array (FPGA) technology. High speed, very large number of components, large number of supported protocols, and addition of ready-to-use intellectual property cores make programmable devices the preferred choice of implementation and even deployment mass production quantities of Power Electronics. Matlab/Simulink is used for the simulation of the proposed SVPWM algorithm. A Field Programmable Gate Array (FPGA) From Xilinx Inc - Spartan 3E was used at the main of the control electronics. The simulation and experimental results are demonstrated.

Index Terms - Field-programmable gate array (FPGA), four switch three phase inverters (B4, FSTPI), six switch three phase inverters (B6, SSTPI), space vector PWM, VHDL.

I. I NTRODUCTION

Three phase variable speed drives for asynchronous motors have been used more and more, especially in energy saving drive applications for fans, pumps, air compressors… In many cases, the cost reduction is an important target for the drive.

To reduce number of power semiconductor devices in a three phase voltage inverter, where there are only 4 switches, were proposed different control methods. One of them is [1], which presents a new space vector PWM algorithm for four switch three phase inverters (B4, FSTPI) based on the one for six switch three phase inverters.

The rapid development in high-performance low-cost digital signal processors (DSP’s) [2], [3] has encouraged research on digital PWM control [4], [5] and digital current control [6] - typical control architecture of a DSP-based ac drive is presented. However, generating PWM gating signals and current control loops requires a high sampling rate to achieve a wide bandwidth performance. Therefore most computation resources of the DSP must be devoted to generating the PWM signals and executing of current control

algorithms [7]. As a result, only limited functions are left for other control loops and functions and complicate the design process enormously [8].

Recently, the FPGA devices have been improved and their application has expanded from prototyping tasks to telecommunication, image and sound processing and many others. The properties of the algorithm processing, such as capability of performing real parallel calculations combined with solutions’ flexibility, are probably the main reasons for applying the FPGA to many technical domains. Many available matrices contain, specialized digital signal processing blocks capable of performing hardware multiplication with accumulation, and block providing with the advanced input-output configuration with digitally controlled impedance feature. The possibility of developing a real hardware implementation of the signal processing algorithms is also a great merit [9][10]

The paper presents the application of FPGA (Spartan 3E from Xilinx, Inс) to realize the SVPWM technique for B4 inverter (FSTP) modeled on the basis of a B6 by using the principle of similarity and revealing perspective solution for the PWM in the zone of overmodulation when the PWM is quite complicated due to the nonlinear character of modulation in this extended zone. The principal control schema is presented in Fig.1.

Fig.1. Four switch three phase inverter (FSTPI) is based on FPGA II. A ^NALYSIS O ^F S ^PACE V ^OLTAGE V ^ECTORS

According to the scheme in Fig.2 the switching status is

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represented by binary variables S1 to S4, which are set to “1”

when the switch is closed and “0” when open.

4

1

1

+S =

S ; S

₃

+S

₂

= 1 (1) Phase to common point voltage depends on the turning off signal for the switch:

( ²

1

¹ ) ₂ ^;

0

( ²

3

¹ ) ₂ ^;

0

^{0 ;}

0

= − ⋅ = − ⋅

c

=

dc b

dc

a

V V

S V V

S

V (2)

Combinations of switching S1-S4 result in 4 general space vectors V G

₁

V G

₄

→ (Table 1).

Fig.2. Sectors used in conventional SVPWM methods for B4 TABLE I

C

OMBINATIONS OF

S

WITCHINGS AND

V

OLTAGE

S

PACE

V

ECTORS

III. M ^ODIFIED S ^VPWM A ^PPROACH F ^OR B4 I ^NVERTER SVPWM methods presented in papers [11, 12, 13, 14, 15]

are based on the formation of the reference vector on the plan αβ which is divided into four sectors (sector I...IV). The active vectors and their duration in one sampling interval are selected and calculated on the basis of the required Vref location respective for these sectors (fig.3).

The modified SVPWM method proposed in this paper is based on [1], where is used a principle of similarity of the one for B6 inverters. The plan αβ is divided into 6 sectors and the formation of Vref is done similarly as for B6. This facilitates the calculation for B4 and some issues for B6 can be applied for B4 thanks to this proposed approach.

To simulate 6 non-zero vectors in B6, in this proposed method, beside the two V1 and V3, we use the effective vectors V23M, V34M, V41M and V12M. These vectors are formed as equations (3)

Fig.3. SVPWM method proposed for B4 on the principle of similarity B6

( ) ( )

(

^{4 1}

)

¹²

(

^{1 2}

)

³

41

3 2 4

3 34

0 3

2 23

3 2

; 1 3 2

1

3 ; 2

; 1 3 2

1

π π

π

dc j M

dc j M

dc j M

dc j M

V e V V V

V e V V V

V e V V V

V e V V V

=

−

+

=

= +

=

= +

=

= +

=

G G G

G G G

G G G

G G G

(3)

To simulate zero vectors of B6, we use the effective V0M:

( ) ^;

2 1

3 1

0

V V

V G

_M

G G

+

= or ^{V G}

^0M

⁼ ₂ ¹ ( ^{V G}

²

^{+ V G}

⁴

) ^; (4) The similarity between space vectors of B4 (Fig.4) and B6 (Fig.5) is presented in Table 2.

Fig.4. Basic space vectors in B4 inverter

Fig.5. Basic space vectors in B6 inverter.

TABLE II

S

IMILARITY BETWEEN

S

PACE

V

ECTORS OF

B4

AND

B6

The base vectors in each sector used to form the required

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space vector Vref is presented in Table 3.

T ABLE III .

V ECTORS USED IN THE S ^PACE V ^ECTOR M ^ODULATION B6 & B4

Fig.6 and Fig.7 presents pulse patterns for switching in the proposed method for six sectors.

Fig.6. Pulse patterns for switching in the proposed method (For sectors I, V, VI)

Fig.7. Pulse patterns for switching in the proposed method (Sectors II, III, IV)

Below we will describe the space vector modulation for B4 inverter based on the modulation for B6 with the principle of similarity: The required voltage space vector rotates in a hexagon and the space vector modulation is based on the formation of three voltage vectors in sequence in one sampling interval Ts so that the average output voltage meets the requirement. The calculations of the switching states in B6 and B4 are as follows for ½ Ts [10]:

( )

( )

y x s z

s y

s x

t t T t

MT t

MT t

−

−

=

=

−

=

2 /

; 3 sin

; 3 / 3 sin

π α

α π π

(5)

Where:

tx - duration for vector Vx ty - duration for vector Vy tz - duration for vector Vz

M – The index of modulation M = V*/V1sw (V* - amplitude of the required voltage vector, V1sw – peak value of six step voltage).

However in B4 inverter since mean vectors tXYM and zero vectors t0M are formed from the two base vectors the duration of base vectors is equal to ½ as for the above

mentioned mean and zero vectors.

It can be used, for example, the effective vectors V23M, V3, V0M for sector I, where V23M, V0M are defined as (11):

( ) ( )

; 2

; 2

; 2 2

; 2

/

; 3 sin

; 3 / 3 sin

0 1 0 3 23 3 23 2

3 23

3 23

f z f z f m f m

f f s of z

s f

y s

f x

t t t t

t t t t

t t T t t

MT t

t MT

t t

=

=

=

=

−

−

=

=

=

=

−

=

= α

α π π π

(6)

Thus the total durations for base vectors V1, V2, V3 are:

z m f V

m V

z V

t t t t

t t

t t

3 3 3 3

2 2

1 1

;

;

+ +

=

=

= (7)

Similarly we can calculate the space vector modulation for the other sectors. The calculation results are shown in Table IV.

T ABLE IV .

V ^ECTOR D URATIONS IN THE P ^ROPOSED S ^VPWM M ^ETHOD

Sector I Sector II

( )

( )

; 2 2

2 ; 2 ;

; 2

/

; 3 sin

; 3 / 3 sin

0 1 0 3

23 3 23 2

3 23 3

23

f z f z

f m f m

f f s of z

s f

y

s f

x

t t t t

t t t t

t t T t t

MT t

t

MT t

t

=

=

=

=

−

−

=

=

=

=

−

=

= π α

α

π π ( )

( )

; 2 2

2 ; 2 ;

; 2

/

; 3 sin

; 3 / 3 sin

0 1 0 3

34 4 34 3

34 3 34

3

f z f z

f m f m

f f s of z

s f

y

s f

x

t t t t

t t t t

t t T t t

MT t

t

MT t

t

=

=

=

=

−

−

=

=

=

=

−

=

= π α

α π π

z m f V

m V

z V

t t t t

t t

t t

3 3 3 3

2 2

1 1

+ +

=

=

=

z m f V

m V

z V

t t t t

t t

t t

3 3 3 3

4 4

1 1

+ +

=

=

=

Sector III Sector IV

( )

( )

; 2 2

2 ;

2 ;

; 2 2

; 2

/

; 3 sin

; 3 / 3 sin

0 1 0 3

41 1

41 34 4 34 3

41 34 41

34

f z f z

f m

f f m f m

f f s of z

s f

y

s f

x

t t t t t t

t t t

t t

t t T t t

MT t

t

MT t

t

=

=

=

+

=

=

−

−

=

=

=

=

−

=

= π α

α

π π ( )

( )

; 2 2

2 ; 2 ;

; 2

/

; 3 sin

; 3 / 3 sin

0 1 0 3

41 1 41 4

1 41 1

41

f z f z

f m f m

f f s of z

s f

y

s f

x

t t t t

t t t t

t t T t t

MT t

t

MT t

t

=

=

=

=

−

−

=

=

=

=

−

=

= π α

α π π

z m V

m V

z m V

t t t

t t

t t t

3 3 3

4 4

1 1 1

+

=

= +

=

z V

m V

z m f V

t t

t t

t t t t

3 3

4 4

1 1 1 1

=

=

+ +

=

Sector V Sector VI

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( ) ( )

; 2 2

2 ; 2 ;

; 2

/

; 3 sin

; 3 / 3 sin

0 1 0 3

12 2 12 1

12 1 12

1

f z f z

f m f m

f f s of z

s f

y

s f

x

t t t t

t t t t

t t T t t

MT t

t

MT t

t

=

=

=

=

−

−

=

=

=

=

−

=

= π α

α

π π ( )

( )

; 2 2

2

2 ;

; 2 2

; 2

/

; 3 sin

; 3 / 3 sin

0 1 0 3

23 3

23 12 2 12 1

23 12 23

12

f z f z

f m

f f m f m

f f s of z

s f

y

s f

x

t t t t t t

t t t

t t

t t T t t

MT t

t

MT t

t

=

=

=

+

=

=

−

−

=

=

=

=

−

=

= π α

α π π

z V

m V

z m f V

t t

t t

t t t t

3 3

2 2

1 1 1 1

=

=

+ +

=

z m V

m V

z m V

t t t

t t

t t t

3 3 3

2 2

1 1 1

+

=

= +

=

IV. S IMULATION OF P ROPOSED S VPWM FOR B4

Matlab/Simulink is used for the simulation of the proposed SVPWM DC voltage Vdc = 300V. Output voltage fundamental harmonic f = 25Hz. Switching frequency fsw = 4.8 kHz. The load parameter is R=20Ω; L=40 mH. The simulation is done for a case modulation index M = 0.7.

The phase voltage, line voltage waveforms, the load phase current and the harmonic spectrum of line voltage are shown in Fig. 8-11 respectively. The simulation results demonstrate the excellent performance of the proposed SVPWM for B4 .

Fig.8. Phase voltage waveform (M=0.7).

Fig.9. The load phase current (M=0.7)

Fig.10. Line voltage waveform (M=0.7).

Fig.11. The harmonic spectrum of line voltage

V. H ^ARDWARE I MPLEMENTATION S ^{VPWM FOR} B4 U ^SING F PGA .

The experimental tests were performed with the aid of the Starter Kit Xilinx Spartan 3E with a chip XC3S500E, that has around 10 000 logic gates and consists 1164 Configurable Logic Blocks (CLBs), 10476 sell, 500 Kbit Data System Gates, 360 Kbit data RAM, 320 pins 232 User I/O Blocks (I/O Blocks), 8 pulse clocks with frequency 300MHz [16]. The scheme of this experimental setup is presented in Fig.12.

Fig.12. Block diagram of B4 Power circuit

It includes DC link from three phase diode-bridge rectifier, a power circuit, a load and a controller (control electronics).

The Power Circuit is constructed using 4 IGBTs FGL60N100BNTD from Fairchild Semiconductor with rating voltage 1000V, current 60A [17]. The Isolation and Driver Block is designed from Gate Drive Optocoupler HCPL 3120 with a maximum switching speed 500ns. The load used in this case is represented by resistive (R=20 Ω) and inductive (R=20 Ω and L=75mH). The DC link voltage was adjusted at

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100V-200V, and the split capacitors are rated at 1000 μF.

Fig.13. Functional block diagram of programmable FPGA-SVPWM for B4 A. Xilinx FPGA design

The functional block diagram of control algorithm developed for implementation of Xilinx to produce switching pattern for B4 operating is shown in Fig.13, that depicts the block diagram of a proposed programmable FPGA-based SVPWM. This design consist command registers for settings of the load voltage’s frequency, amplitude, the switching frequency of the PWM, and the delay time for the power device. To simplify the interface circuit, commands to these registers are routed through a common data bus and decoded by a command mode decoder. The control parameters can be set by externally connected hardware, such digital switches.

The internals of the designed SVPWM consist of a sin-table address decoder, a duty-ratio calculator, a PWM waveform generator, and a programmable delay-time controller.

The programming algorithms SVPWM for B4 in VHDL is used, where load voltage’s frequency is setting by externally 4-bit data input, the magnitude modulator is getting from control principle V/f=const. An external main clock was used as the clocking signal for the FPGA due to frequency of carrier signal used in this work. A ten bit up- down counter is clocked at 50 MHz to produce a carrier frequency at 31 kHz. The sin/cos and sectors can be obtained from multiplication of the modulating signal from the look-up table (ROM) with an external basic frequency input. Finally, the PWM gating signals are inserted with adjustable time delay to protect the phase legs from short circuiting.

B. Experimental results

To realize the proposed SVPWM scheme, cost considerations led to selecting an SRAM-based FPGA Spartan 3E XC3S500E from Xilinx, Inc. for implementing of the SVPWM. Xilinx also provides ISE 8.2i tools for the development of ASIC’s employing FPGA’s. The simplicity in the interface circuit design illustrates its feasibility for practical applications. To observe experimental results Tektronic Oscilloscope 200MHz, 4 channels is used.

Fig.14 – Fig.21 illustrate the experimental results of integrating the voltage vector of the SVPWM for B4 gating signals at various operation frequencies. The output

fundamental frequency can be adjusted from 1Hz to 70 Hz.

The PWM switching frequency can be set from 400Hz to 35 kHz. Experimental results show the constructed SVPWM IC can generate a wide range of output frequencies with controlled fundamental voltage.

1. Case study 1: The fundamental harmonic of output voltages is 50Hz with PWM frequency 5.5 kHz. Fig. 14- 17 shows the phase voltages; line voltages waveforms of Vab, and harmonic of a phase load current ia.

Fig.14. Phase load voltages

Fig.15. Line load voltage

Fig.16. The harmonic spectrum of line voltage.

Fig.17. Phase load current.

2. Case study 2: The fundamental harmonic of output voltages is 50Hz with PWM frequency 27.5 kHz. Fig. 18- 21 shows the phase voltages; line voltages waveforms of Vab, and a harmonic of a phase load current ia:

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Fig.18. Phase load voltages

Fig.19. Line load voltage

Fig.20. The harmonic spectrum of line voltage.

Fig.21. Phase load current VI. C ONCLUSIONS

The proposed SVPWM in this paper is based on the one for six switch three phase inverters (B6, SSTP) using principle of similarity where the αβ plan is divided into 6 sectors and the formation of the required reference voltage space vector is done in the same way as for B6 by using the additional effective vectors. This facilitates the SVPWM calculation for B4 and some studies on B6 can be applied for B4 as well through this proposed approach. The implementation of the proposed SVPWM is done by simulation and in experiment to serve the practical production of the cost effective inverters in the future.

The presented experimental results shows that the extremely fast FPGA computation time allows obtaining much higher throughput and overcoming the typical bottlenecks of DSP sequential algorithms mentioned at the beginning. Applying FPGA for power electronics control seems is an interesting alternative to the recently used digital signal processors. It should be emphasized that such high processing frequency (low loop period) as in the proposed FPGA application.

An application FPGA for SVPWM technique allow to prove Power Electronic Devise, such voltage source inverters and increase switching frequency of power electronic switches.

R ^EFERENCES

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[16] Spartan-3E FPGA Family: Complete Data Sheet Xilinx Inc DS312 April 18, 2008.

[17] FGL60N100BNTD datasheet from Fairchild Semiconductor Corporation 2004.

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