Electronics III

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(1)Electronics III. by. Dr. Steve Tu Rm SF726C E-mail : [email protected]. Department of Electronic Engineering Fu Jen Catholic University Fall 2008 (p1).

(2) Outline – Introduction 1. Operational Amplifiers and Data Converters.. 2 Filters. Signal Generators and Waveform-Shaping 3. Circuits. Output Stages and Power Amplifiers.. (p2).

(3) Recommended Books – 1. Sedra and Smith, “Microelectronic Circuits”,5th edition Principal textbook for this course.. 2. B. Razavi, 2001 “Design of Analog CMOS Integrated Circuits”, McGRAW-HILL Very concise and well-written in CMOS analog circuit design.. Grading Policy – 1. Three exams and the dates are NEGOTIABLE !! ( 30% x 3) 2. Interaction with the lecturer. ( 10% ). (p3).

(4) R → high 1/λId. gm. Transfer conductance. ⇒ Transfer Resistance ⇒ Transistor. GENERAL TRANSISTOR. R → high. R → low. vo / vin = (io / vin)(vo / io) = gm R BJT vo3 / vi2 = -gmrce vo1 / vi2 = gm/gm vo3 / vo1 = gmrce. CE CC CB. FET vo3 / vi2 = -gmrds= -gm/go CS vo1 / vi2 = gm/gm = 1 CD vo3 / vo1 = gmrds = gm /go CG. Ea : Early voltage, in the range of 70V to 120V. VT : Thermal voltage, 26mV at room temperature ( 3000K ) ( Source reference : “High frequency CMOS and bipolar analog design” by Prof. C. Toumazou, Imperial College London, UK. 1998 ). (p4).

(5) Lecture 2a – CMOS OP AMP A FEEL FOR TYPICAL OP-AMP PERFORMANCE. CMOS. BIPOLAR. Differential Voltage Gain (AV). 80dB. 100dB. Common-mode Rejection Ratio (CMRR). 80dB. 100dB. Input Bias Current (IB). ≈0. 100nA. Input Offset Voltage (VOS). ±20mV. ±5mV. Differential Input Resistance (Rin) 1014 Ω. 107 Ω. Output Resistance (Rout). 100 Ω. 1KΩ (BUFF) 100KΩ (UNBUFF). (p1).

(6) The Two-Stage CMOS OP AMP –. . The circuit consists of two gain stages. Namely, differential pair Q1, Q2 which provides voltage gain 20 V/V ~ 60 V/V and current mirror load Q3, Q4.. . The differential pair is biased by current source Q5, which is one of the two output transistors of the current mirror formed by Q8, Q5, and Q7.. . The second gain stage consists of the common-source transistor Q6 and its current-source load Q7. The second stage can provide a gain of 50 V/V to 80 V/V.. . The op amp can operate in a stable fashion by introducing a pole at a relatively low frequency and arranging for it as a dominate pole. In a circuit, it can be implemented using a compensation capacitance CC connected in the negativefeedback path of the second-stage amplifying transistor Q6. ( why ???? ). . Recall that systematic output dc offset can be eliminated by following the constraint,. (W / L) 6 (W / L) 7 =2 (W / L) 4 (W / L) 5. (p2).

(7) 1.. Input Common-Mode Range (ICMR) and Output Swing –. (when the two input terminals are tied together and connected to a voltage VICM ) . First of all, find the lowest value of VICM, ( FACT: Q1 and Q2 must be in sat. ). ⇒. Lowest value of VICM must not be lower than the voltage at the drain of Q1 by more than ⏐Vtp⏐,. ⇒. VICM ≥ −VSS + Vtn + VOV 3 − Vtp. . The highest value of VICM should ensure that Q5 remains in sat.. ⇒. The voltage across Q5, VSD5, must not decrease below ⏐VOV5⏐. ⇒. VICM ≤ VDD − VOV 5 − VSG1. ⇒. VICM ≤ VDD − VOV 5 − Vtp − VOV 1. . Combining the two inequalities yields,. − VSS + VOV 3 + Vtn − Vtp ≤ VICM ≤ VDD − Vtp − VOV 1 − VOV 5 . Output signal swing is limited at the lower end by the need to keep Q6 sat. and at the upper end by the need to keep Q7 sat.. ⇒. − VSS + VOV 6 ≤ vo ≤ VDD − VOV 7. 2.. Voltage Gain –. . We can model the small-signal operation with transconduction amplifiers for the two-stage OP AMP.. . The input resistance is practically infinite, Rin = ∞ and the first-stage transconduction Gm1 = gm1 = gm2.. (p3).

(8) Since Q1 and Q2 are operated at equal bias currents I/2 and equal overdrive voltages, VOV1 = VOV2, ⇒. Gm1 = 2(I/2)/VOV1 = I/VOV1. Resistance R1 is the output resistance of the first stage, ⇒. R1 = ro2 || ro4. where ro2 = |VA2|/(I/2) and ro4 = |VA4|/(I/2). The gain of the first stage is thus,. A1 = −Gm1 R1 = − g m1 (ro 2 // ro 4 ) = − ⇒. ⎡ 1 1 ⎤ + ⎢ ⎥ V V A 2 A 4 ⎣ ⎦. 2 VOV 1. A1 is increased by operating Q1 and Q2 at a low overdrive voltage and by choosing a longer channel length to obtain larger Early voltages.. ⇒. Both actions degrade the frequency response. ( Recall the requirements at high frequency operation !! ). . The second–stage transconduction Gm2 is given by and the output resistance of the second stage, where. ro 6 =. VA6 I D6. and. ro 7 =. VA7 I D7. =. Gm 2 = g m 6 =. 2I D6 VOV 6. R2 = ro 6 // ro 7. VA7 I D6. The voltage gain of the second stage is therefore,. A2 = −Gm 2 R2 = − g m 6 (ro 6 // ro 7 ) = −. 2 VOV 6. ⎡ 1 1 ⎤ + ⎢ ⎥ V V A 6 A 7 ⎣ ⎦. (p4).

(9) The overall voltage gain is thus,. Av = A1 A2 = Gm1 R1Gm 2 R2 = g m1 (ro 2 // ro 4 ) g m 6 (ro 6 // ro 7 ) Notice that Av will be in the range of 500 V/V to 5000 V/V. . The output resistance of the op amp is the output resistance of the second stage,. Ro = ro 6 // ro 7. which it can be large ( tens-of-kilohms range ). . Note that since on-chip CMOS op amps are rarely required to drive heavy loads, the large open-loop output resistance is usually not an important issue.. 3.. Frequency Response –. . Refer to the equivalent small-signal circuit, C1 is the total capacitance of the output node of the first stage, thus C1 = Cgd2 + Cdb2 + Cgd4 + Cdb4 + Cgs6 and C2 = Cdb6 + Cdb7 + Cgd7 + CL. . where CL is the load capacitance.. The CMOS op amp has two poles and a positive real-axis zero with the following approximate frequencies,. f P1 ≅. 1 2πR1Gm 2 R2CC. Gm 2 2πC2 G f Z ≅ m2 2πCC. f P2 ≅. . Here, fP1 is the dominant pole ( why?? ) and the unity-gain frequency ft is given by,. f t = Av f P1 =. Gm1 2πCC. (p5).

(10) which must be lower than fp2 and fZ and it implies that. Gm1 Gm 2 < CC C2 . and. Gm1 < Gm 2. Simplified Equivalent Circuit – The uniform –20dB/decade gain rolloff suggests that the op amp can be represented by the simplified equivalent shown in the following figure.. this simplification is based on the assumption that the gain of the second stage is large and hence a virtual ground appears at the input terminal of the second stage. . Phase Marge – The pole-splitting frequency compensation scheme provides a dominant low-frequency pole with frequency fP1 and shifts the second pole beyond ft , thus (1). Phase lag due to fP1 is 900 (2). Phase lag due to fP2 is. tan –1(ft / fP2). (3). Phase lag due to the right-half-plane zero is tan –1(ft / fZ) therefore, the phase lag at f = ft will be ⇒. φtotal = 900 +tan –1(ft / fP2)+tan –1(ft / fZ). and the phase margin will be ⇒. Phase margin = 1800 - φtotal = 900 -tan –1(ft / fP2)-tan –1(ft / fZ). (p6).

(11) . Notice that we still have a zero which provides additional phase lag. Let’s investigate with the following figure.. The new location of the transmission zero can be found by setting Vo = 0 and now the current through CC will be Vi2 / (R+1/sCC) and a node equation at the output yields. Vi 2 1 R+ sCC. = Gm 2Vi 2. Thus the zero is now at. ⎛ 1 ⎞ s = 1 / CC ⎜⎜ − R ⎟⎟ ⎝ Gm 2 ⎠. By selecting R = 1/Gm2, we can place the zero at infinite frequency.. . Slew Rate – Consider the unity-gain follower with a step of 1V applied at the input as shown in the following figure.. (p7).

(12) As we know its output will not change in zero time, immediately after the input is applied, the entire value of the step will appear as a differential signal between the two input terminals. ⇒. Such a large signal will exceed the voltage required to turn off one side of the pair and switch the entire bias current I to the other side. The current I will be pulled from CC as shown in the following left figure. The output voltage will be a ramp with a slope of I/CC .. vo (t ) =. I t CC. and the slew rate is given by. SR =. I CC. (p8).

(13) The Folded-Cascode CMOS OP AMP. (p9).

(14) . The Circuit – Q1 and Q2 form the differential pair, and Q3 and Q4 are the cascode transistors. Note that each of the transistor pairs Q1, Q3 and Q2, Q4 acts as a folded-cascode amplifier. Moreover, we may select IB = I to force all transistors operating at the same bias current of I/2. A more complete circuit is shown in the following figure. Here we replace the bias current sources with active devices ( Q9, Q10, and Q11 ). (p10).

(15) 1.. Input Common-Mode Range and Output Voltage Swing –. (when the two input terminals are tied together and connected to a voltage VICM ) . First of all, the maximum value of VICM is limited by the Q1, Q2 operate in saturation at all times. Assuming that Q9 and Q10 are operated at the edge of saturation, VICMmax will be. VICM max = VDD − VOV 9 + Vtn Note that it can be larger than VDD, which indicates that we have obtained significant improvement over the case of two-stage circuit. . The minimum value of VICM is the same as in the case of the two-stage circuit,. VICM min = −VSS + VOV 11 + VOV 1 + Vtn Thus, we obtain the following relationship,. − VSS + VOV 11 + VOV 1 + Vtn ≤ VICM ≤ VDD − VOV 9 + Vtn . The upper limit of vo will be. v o max = V DD − V OV 10 − V OV. 4. provided we select the value of VBIAS1 so that Q10 operates at the edge of sat.. vo min = −VSS + VOV 7 + VOV 5 + Vtn. . The lowest possible vo will be. 2.. Voltage Gain –. . The folded-cascode op amp is a transconductance amplifier ( also called Operational Transconductance Amplifier ( OTA) ) with 1. Input resistance - ∞ 2. Transconductance – Gm 3. Output resistance – Ro see the right figure for its small-signal equivalent.. (p11).

(16) . Gm is equal to gm of each of the two transistors. Thus, Gm = gm1 = gm2 Threefore,. . Gm =. I 2( I / 2) = VOV 1 VOV 1. The output resistance Ro = Ro4 // Ro6 in which Ro4 ≅ ( gm4ro4)(ro2 //ro10) and Ro6 ≅ gm6ro6ro8 Therefore, Ro =[gm4ro4(ro2 //ro10)]// (gm6ro6ro8). . The dc gain can now be found, Av = GmRo.. 3.. Frequency Response –. . Since CL is usually large, the pole at the output becomes dominant.. From the small-signal equivalent circuit, we can obtain Vo Gm Ro = Vid 1 + sC L Ro 1 fP = The dominant pole frequency is 2πC L Ro G The unity–gain frequency will be f t = Gm Ro f P = m 2πC L Notice that we may compare the effects of increasing the load capacitance on the . operation of the two-stage op-amp circuits. 1.. Two-stage op amp – CL ↑ , phase margin ↓. 2.. Folded-cascode op amp – CL ↑ , f t ↓, phase margin ↑. 4. Slew Rate – When a large differential input signal is applied, Q3 will now carry a current (IB-I) and Q4 will conduct a current IB. The current mirror will see an input current of (IB-I) through Q5 and Q7 and thus its output current in the drain of Q6 will be (IB-I) and the current flows into CL will be I4 –I6 = I. Thus , the slew rate will be. SR =. I CL. (p12).

(17) 5.. Increasing the ICMR: Rail-to-Rail Input Operation –. Basic Idea: In the previously mentioned configuration, we know that the upper limit on the ICMR exceeds the supply voltage VDD, the lower limit is significantly lower than VSS. The opposite situation occurs if the input differential amplifier is made up of PMOS transistors.. ⇒. An NMOS and a PMOS differential pair placed in parallel shall provide an input stage with a common-mode range that exceeds the power supply voltage in both directions.. ⇒. This is known as rail-to-rail input operation.. See the following figure,. . Each of the current increments indicated is equal to Gm(Vid/2) where Gm = gm1 = gm2= gm3 = gm4. Thus the total current feeding each of the two output nodes will be GmVid.. . If the output resistance between each of the two nodes and ground is Ro, the output voltage will be Vo = 2GmRoVid and the voltage gain will be Av = 2GmRo.. (p13).

(18) 6.. Increasing the Output Voltage Range: The Wide-Swing Current Mirror –. Current Problem: The cascode current mirror limits the negative swing to [2|VOV|+Vt] above -VSS and positive swing to within 2|VOV| of VDD. See the following figure.. To permit the output voltage at the drain of Q3 to swing as low as 2VOV instead of 2VOV +Vt, we must let the gate of Q3be at Vt +2VOV and thus we connect the gate of Q3 to a bias voltage VBIAS = Vt +2VOV and so we can obtain the output voltage 2VOV with Q3 still in saturation. Now the drain of Q1 is VOV and it is operating at the edge of saturation.. (p14).

(19) Lecture 2b – The 741 Op-Amp Circuit. first stage. second stage. output stage. The 741 op-amp circuit. Q11, Q12, and R5 generate a reference bias current, IREF, Q10, Q9, and Q8 bias the input stage, which is composed of Q1 to Q7. The second gain stage is composed of Q16 and Q17 with Q13 acting as active load. The class AB output stage is formed by Q14 and Q20 with biasing devices Q18 and Q19 and an input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against output short circuit and are normally off.. (p1).

(20) The DC analysis of the 741 input stage.. (p2).

(21) Small-signal analysis of the 741 input stage The small-signal equivalent circuit for the input stage is shown in the following figure.. The differential signal vi applied between the input terminals effectively appears across four equal emitter resistances connected in series - Q1 through Q4. As a result, emitter signal currents flow as indicated in the right figure. Thus, ie =. vi 4re. And the input differential resistance of the op amp can be obtain as Rid = 4 (βN+1)re Refer to the right figure to analyze the equivalent Gm1 of the first stage. We see that the collector signal current of Q5 is about the input current αie. Since Q5 and Q6 are identical and their bases are tied together and equal resistances are connected in their emitter, their collector signal currents must be equal. The output current io is thus given by io = 2αie and G ≡ m1. α io = vi 2re. (p3).

(22) Small-signal analysis of the 741 second stage ( Refer to the textbook and try to find out the equivalent values to fit the following model ). ( voltage input, current output model ). By inspection, Ri2 = ( β16 + 1 )[ re16 + R9 // ( β17 + 1 )( re17 + R8 )] Gm can be obtained by short-circuiting the output terminal of the second stage to ground. Thus, refer to the figure, we will obtain. ic 17 = β ib 17 = α ie17 = where vb17 = vi 2. R9 // Ri17 ( R9 // Ri17 ) + re16. α v b 17 re17 + R 8. ,. Ri17 = ( β17 + 1)(re17 + R8 ). Thus, the transconduction is going to be Gm 2 ≡. ic17 vi 2. The output resistance is given by Ro2 = Ro13B // Ro17 , where Ro13B = ro13B since Q13B’s base and emitter are connected to ground. Moreover, the resistance between the base of Q17 and ground is relatively small, we can assume that the base is grounded. Thus, refer to the figure, we obtain Ro17 = ro17[1 + gm( R8 // rπ )]. (p4).

(23) Analysis of the 741 output stage The output stage is of class AB, which composed of Q18 and Q19 and R10 providing the bias of the output transistors Q14 and Q20. The output stage is driven by an emitter follower Q23 which provides added buffering.. Output Voltage Limits The maximum positive output voltage is limited by the saturation of the current-source transistor Q13A, that is, Vomax = VCC – VECsat – VBE14 The minimum output voltage is limited by the saturation of Q17, that is, Vomin = -VEE + VCEsat + VEB23 + VEB20. (p5).

(24) Small-Signal Model. The voltage gain of the second stage is A2 ≡ where Ri 3 ≈ β 23 ( β 20 RL // ro13 A ). vi 3 Ri 3 = −Gm 2 Ro 2 vi 2 Ri 3 + Ro 2. vo vo 2. Define μ as the open-circuit voltage gain of the output stage, μ =. RL = ∞. According to RL is infinite, the resistance in the emitter of Q23 will be very large and thus the gain of Q23 will be nearly unity and the input resistance of Q23 will be very large. In other words, μ is near 1. The output resistance of the op amp can be determined from Ro23. (p6).

(25) which is given by Ro 23 =. Ro 2 + re 23 β 23 + 1. in parallel with the series combination of ro13A and the resistance of the Q18-19 network ( near ro13A alone ) In addition, since ro13A is much larger than Ro23, thus we obtain ( near 75 ohms ). Ro =. Ro 23 + re 20 β 20 + 1. Output Short-Circuit Protection Output terminal is short-circuited to one of the power supplies ⇒ Conduct a large amount of current ⇒ Result in sufficient heating to cause burnout of the IC. [Solution] – Limiting the current in the output transistors in the event of a short circuit. See the figure, here we got R6 and Q15 limit the current that could flow out of Q14 in the event of short circuit. For example, if the emitter current of Q14 exceeds near 20mA, the voltage drop across R6 exceeds 540mV, which turns on Q15. As Q15 turns on, its collector takes away some of the current supplied by Q13A, thus reducing the base current of Q14.. (p7).

(26) Gain and Frequency Response of the 741 Small-Signal Gain The overall small-signal gain is the cascade of the equivalent circuits derived from the three op-amp stages which can be expressed as ( see the following macro-model ) v o vi 2 v o 2 v o RL = = −Gm1 ( Ro1 // Ri 2 )(−Gm 2 Ro 2 ) μ vi vi vi 2 v o 2 RL + Ro. Frequency Response – The 741 is an internally compensated op amp, which employs the Miller compensation technique to introduce a dominant lowfrequency pole. By using Miller theorem, the effective capacitive capacitance due to CC is Ci = Cc (1 + A2 ) The total resistance between the node and ground is Rt = ( Ro1//Ri2 ) Thus the dominant pole fp is given by ______________________ and the unity-gain bandwidth ft is given by _________________. (p8).

(27) Lecture 2c – Data Converters Background Analog ? Digital ?? Here we know that some of those obtained physical signals are naturally in analog form such as the signal from instrumentation systems. Usually, these signals need to be filtered so to eliminate interference.. However, further signal processing is usually required in order to obtain a complex control function. The signal processing can be performed in the analog domain. However, an attractive alternative still exists.. In other words, why we don’t convert analog form to digital form followed some initial analog processing, and then use economical, accurate, and convenient digital IC’s to perform digital signal processing.. Once digital signal processing has been carried out, we may display the result in digital form. Alternatively, we may require an analog output ( such as in a telecommunications system ), then obviously we need to convert the digital signal back to an analog form.. (p1).

(28) Sampling of Analog Signals – The principle underlying digital signal processing is that of sampling the analog signal, which the conceptual form is shown in the following figure.. The switch shown closes periodically under the control of a periodic pulse signal ( clock ) and the samples obtained are stored on the capacitor. The circuit is known as a sample-and-hold ( S/H) circuit.. (p2).

(29) Between the sampling intervals – during the hold intervals, the voltage level on the capacitor represents the signal samples. Each of these voltage levels is then fed to the input of an A/D converter which provides an N-bit binary number proportional to the value of signal sample.. Signal Quantization – Consider an analog signal ranging from 0 to 10V. If we employ 4 bits to represent the output, we can obtain 16 different values, 0 to 15; it follows that the resolution of our conversion will be 10V/15 = 2/3V. e.g. 0V -> 0000, 2/3V -> 0001, 10V -> 1111 Notice that all of the sample numbers were multiples of the basic increment 2/3V here. How about , say 6.2V analog level ? It will fall between 18/3 and 20/3. Since it closer to 18/3, so we treat it as 6V and code it as 1001. Therefore, the process is called quantization. Note that we also introduce errors in the process, which is called quantization errors. Using more bits to represent an analog signal can reduce the errors, but requires more complex circuitry.. (p3).

(30) D/A Converter Circuits– 1. Binary-Weighted Resistors. The circuit comprises a reference voltage Vref, N binary-weighted resistors R, 2R, 4R, 8R, … 2N-1R, N single-pole double-throw switches S1, S2,…. SN, and an op-amp together with its feedback resistance Rf = R/2. The switches are controlled by an N-bit digital input word D, where. D=. bN b1 b2 + + + ... 21 2 2 2N. bN is the LSB and b1 is the MSB, b1 controls switch S1, b2 controls S2…. Notice that the current through each resistor remains constant and each switch simply controls where its corresponding current goes to ground ( position 1 ) or to virtual ground ( position 2 ). (p4).

(31) The currents flowing into the virtual ground add up , and the sum flows through the feedback resistance Rf . The total current io is therefore given by. io =. Vref R. b1 +. Thus, io =. Vref 2R. 2Vref R. b2 + ..... +. D. Vref 2 N −1 R. bN =. 2Vref ⎛ b1 b2 b ⎞ ⎜ 1 + 2 + .... + NN ⎟ R ⎝2 2 2 ⎠. and the output voltage vo is given by. vo = −io R f = −Vref D which is directly proportional to the digital word D.. The disadvantage of the binary-weighted resistor network is that for a large number of bits ( N > 4 ), the spread between the smallest and largest resistances becomes quite large, which implies difficulties in maintaining accuracy in resistor values.. (p5).

(32) 2. R-2R Ladders. For N > 4, the network is usually preferred to the binaryweighted scheme since it shows small spread in resistance values. The resistance to the right of each ladder node is equal to 2R, thus the current flowing to the right , away from each , is equal to the current flowing downward to the ground, and TWICE that current flows into the node from the left side. Thus,. I1 = 2 I 2 = 4 I 3 = ..... = 2 N −1 I N. and the output current io is given by. io =. Vref R. D. A Practical Circuit Implementation The practical circuit implementation of the DAC utilizing an R2R ladder is shown in the next page, which the circuit uses BJT’s to generate binary-weighted constant currents I1, I2, I3…..,IN which are switched between ground and virtual ground of an output summing op-amp .. (p6).

(33) For the rightmost two transistors QN and Qt, their emitter currents will be equal and are denoted IN/α if they are matched. In addition, the voltage between the base line of the BJT’s and node N will be. ⎛I ⎞ VBN = VBEN + ⎜ N ⎟2 R ⎝α ⎠. The voltage between node B and node ( N-1 ) will be. 4I ⎛ 2I ⎞ VB , N −1 = VBN + ⎜ N ⎟ R = VBE N + N R α ⎝ α ⎠ Since two transistors have equal VBE drops if their junction areas are scaled in the same proportion as their currents. Therefore,. I1 = 2 I 2 = 4 I 3 = .... = 2 N −1 I N. (p7).

(34) Let’s take a look at the op-amp A1, since a virtual ground appears at the collector of Qref, which forces the collector current Iref = Vref / Rref, and if Q1 and Qref are matched, the collector currents will be equal, I1 = Iref. Current Switches – The current switches can be implemented as shown in the following,. bm. io. Qms. Qmr. Vbias. ( digital input ). Im. The circuit is a differential pair with the base of the reference transistor Qmr connected to a suitable dc voltage Vbias, and the digital signal representing the mth bit bm applied to the base of the other transistor Qms. If the voltage representing bm is higher than Vbias by a few hundred millivolts, Qms will turn on and Qmr will turn off. The bit current Im will flow through Qms and onto the output summing line. On the other hand, when bm is low, Qms will be off and Im flows through Qmr to ground.. (p8).

(35) A/D Converter Circuits– 1. The Feedback-Type Converter. Analog Input vA. Differential comparator. Up/down control. Up/down counter. … vo. Clock 1 2 3 N. N-bit digital output. DAC. The comparator provides an output that assumes one of two distinct values : positive when the difference input signal is positive, and vice versa. The up-down counter can count either up or down depending on the binary level applied at its up-down control terminal. The DAC operates as follows, with a 0 count the D/A converter output Vo will be zero and the output of the comparator will be high, which force the counter to counter in the up direction……. The type of converter is operating slow if it starts from zero.. (p9).

(36) 2. The Dual-Slope A/D Converter. (p10).

(37) 3. The Parallel or Flash Converter. Analog Input VR1. Comparator 1. VR2. Comparator 2. Bit 1. Bit 2 Logic. …. …. Bit N. Comparator 2N-1. VR ( 2 N −1). The fastest A/D conversion scheme ( simultaneous, parallel ). The outputs of the comparators are processed by an encodinglogic block to provide the N bits of the output digital word. A complete conversion can be obtained within one clock cycle. However,. the. price. paid. is. a. rather. complex. circuit. implementation.. (p11).

(38) 4. The Charge-Redistribution Converter. (p12).

(39) Lecture 3 – Filters The oldest technology for realizing filters makes use of inductors and capacitors, and the resulting circuits are called passive LC filters. ( work well in high frequency !! ) However, they are too large to implement filters in low frequencies since recall ω = 1 / LC Furthermore, such inductors are impossible to fabricate in monolithic form and are incompatible with any of the modern techniques for assembling electronic systems. So we need filters which do not require inductors !! The filters studied here are linear circuits represented by the general two-port network and the transfer function can be described as T(s) ≡ Vo(s)/Vi(s). (p1).

(40) Filter Transmission, Types, and Specification The transfer function T(s) is the ratio of the output voltage Vo(s) to the input voltage Vi(s),. T ( s) ≡. Vo ( s ) Vi ( s ). The filter transmission is found by evaluating T(s) for physical frequencies, s = jω, and can be expressed in terms of its magnitude and phase as T ( jω ) = T ( jω ) e jφ (ω ). Gain function –. G (ω ) ≡ 20 log T ( jω ) , dB. Attenuation function – G (ω ) ≡ −20 log T ( jω ) , dB A filter shapes the frequency spectrum of the input signal according to the magnitude of the transfer function T ( jω ) , thus providing an output with a spectrum Vo ( jω ) = T ( jω ) Vi ( jω ) The interest here will be focused on the frequency-selection functions which include four major filter types : low-pass, highpass, bandpass, and bandstop ( band-reject ).. (p2).

(41) Filter Specification – The following figure shows the realistic specifications for the transmission characteristics of a physical low-pass filter.. A physical circuit cannot provide constant transmission at all passband frequencies, the specifications allow for deviation of the passband transmission from the ideal 0dB, but places an upper bound, Amax( dB ) on this deviation. The Amax typically ranges from 0.05 to 3dB. The specifications require the stopband signals to be attenuated by at least Amin ( dB ) relative to the passband signals and it can range from 20 ~ 100dB.. (p3).

(42) The transition band, which provides for a band of frequencies over which the attenuation increases from near 0 dB to Amin, extends from the passband edge ωp to the stopband edge ωs . The ratio ωs /ωp is used as a measure of the sharpness of the lowpass filter response and is called the selectivity factor. So, the transmission of a low-pass filter is specified by 4 parameters : ωp , Amax, ωs , Amin. Notice that the more tightly one specifies a filter, the closer the response of the resulting filter to the ideal, which on the other hand the filter circuit must be of higher order and thus more complex and expensive. Amax is also called passband ripple since the peak ripple is equal to Amax and ωp is called ripple bandwidth. The particular filter response shown ripple also in the stopband and here the ripple peaks all equal and of such a value that the minimum stopband attenuation achieved is equal to Amin. The particular response is said to be equiripple in both the passband and the stopband.. (p4).

(43) Filter Transfer Function The transfer function T(s) can be written as the ratio of two polynomials as. aM s M + aM −1s M −1 + ... + a0 T (s) = s N + bN −1s N −1 + ...b0 Notice that the degree of the denominator, N is the filter order. For the filter circuit to be stable, M ≤ N. The polynomials in the numerator and denominator can be factored, and T(s) can be expressed in the form. T ( s) =. aM ( s − z1 )( s − z 2 )...( s − z M ) ( s − p1 )( s − p2 )...( s − p N ). z1, z2,….zM are the transfer-function zeros ( transmission zeros ) p1, p2,….pN are the transfer-function poles ( natural modes ) Complex zeros and poles must occur in conjugate pairs. The filter transmission characteristic shown on page 3 can be seen to have infinite attenuation at two stopband frequencies: ωl1 and. ωl2 . In addition, we spotted from the figure that the transmission decreases toward -∞ ( infinite attenuation ) as ω approaches ∞, so we know that the filter must have transmission zero(s) at s = ∞. . For a filter circuit to be stable, all its poles must lie in the left half of the s-plane.. (p5).

(44) The typical pole and zero locations for the low-pass filter is shown above. The 5 transmission zeros are at s = ±jωl1, s = ±jωl2, and s = ∞. Let’s also take another example shown on the bottom of page 4. Here the filter has transmission zeros at s = ±jωl1, s = ±jωl2. Because the attenuation decreases toward - ∞ as ω approaches 0 and ∞, the filter has one or more zeros at s= 0 and one or more zeros at s= ∞. A typical pole-zero plot for such a filter is shown on the top of the next page.. (p6).

(45) Let’s consider the following transmission function of a low-pass filter.. T (s) =. aM s N + bN −1s N −1 + ... + b0. It is possible that all the transmission zeros of this filter are at s = ∞ and in this case there are no finite values of ω at which the attenuation is infinite as shown in figure 11.7(a), and such a filter is known as an all-pole filter.. (p7).

(46) Butterworth and Chebyshev Filters – I. The magnitude response of a Butterworth filter.. The magnitude function for an Nth-order Butterworth filter with a passband edge ωp is given by. T ( jω ) =. 1 ⎛ω ⎞ ⎟ 1+ ε 2⎜ ⎜ω ⎟ ⎝ p⎠. 2N. and the maximum variation in passband transmission Amax is given by Amax = 20 log 1 + ε 2 Notice that the first 2N-1 derivatives of |T| relative to ω are zero at ω = 0, which makes the Butterworth response very flat near ω = 0. The degree of passband flatness increases as the order N is increased, which makes the filter response approaches the ideal brick-wall type response.. (p8).

(47) The following figure shows the magnitude response for Butterworth filters of various order with ε = 1. Note that as the order increases, the response approaches the ideal brickwall type transmission.. The poles of an Nth-order Butterworth filter can be determined from the graphical construction shown in the following figures.. ( a ). The general case. (p9).

(48) II. The magnitude response of a Chebyshev filter.. The Chebyshev filter exhibits an equiripple response in the passband and a monotonically decreasing transmission in the stopband. The odd-order filter has |T(0)| = 1 and the even-order filter exhibits its maximum magnitude deviation at ω=0. Notice that in both cases the total number of passband maxima and minima equals the order of the filter N. All the transmission zeros of the Chebyshev filter are at ω = ∞, making it an all-pole filter. Note that the Chebyshev filter provides a more efficient approximation than the Butterworth filter. In other word, for the same order and the same Amax , The former one provides greater stopband attenuation than the latter one. It also means that to meet identical spec., one requires a lower order for the Chebyshev than for the Butterworth filter.. (p10).

(49) First-order and Second-order Filter Functions The simplest filter transfer functions – first and second order, which they can be cascaded to realize a high-order filter. Since the filter poles occur in complex-conjugate pairs, a highorder transfer function T(s) is therefore factored into the product of second-order functions. However, if T(s) is odd, there will also be a first-order function in the factorization. Each of the functions is then realized using one of the op amp-RC circuits, and the resulting blocks are placed in cascade.. The general first-order transfer function is given by T ( s ) = this characterizes a first-order filter with. a1s + a0 s + ω0. (1). A natural mode at s = -ω0 (2). A transmission zero at s = -a0/a1 (3). A high-frequency gain that approaches a1. a0, a1 determine the type of filter ( see the table on the next page ! ). (p11).

(50) (p12).

(51) Second-order Filter Functions The general second-order ( biquadratic ) filter transfer function can be expressed in the standard form. a2 s 2 + a1s + a0 T (s) = 2 2 s + (ω0 / Q) s + ω0 In which ω0 and Q determine the natural modes according to p1, p2 = −. ω0 2Q. ± jω0 1 − (1 / 4Q 2 ). For Q > 0.5, we can obtain complex-conjugate natural modes. Notice that the radial distance of the natural modes is equal to ω0 which is known as the pole frequency and Q determines the distance of the poles from the jω-axis. Also an infinite value for Q locates the poles on the jω-axis and can yield sustained oscillations. The parameter Q is called the pole quality factor, or pole-Q. The transmission zeros are determined by the numerator coefficients, a0, a1, and a2 which determine the type of secondorder filter function. ( LP, HP,….) There are two transmission zeros are at s = ∞ for low-pass case with the transfer function,. a0. T ( s) = s2 + s. ω0 Q. + ω0. 2. (p13).

(52) There are two transmission zeros are at s = 0 for high-pass case with the transfer function,. a2 s 2. T ( s) =. s2 + s. ω0 Q. + ω0. 2. There are two transmission zeros for a bandpass filter function. One is at s = 0 , and the other is at s = ∞. The transfer function can be expressed as. a1s. T ( s) = s2 + s. ω0 Q. + ω0. 2. Note that the magnitude response peak at ω = ω0 . Thus the center frequency of the bandpass filter is equal to the pole frequency ω0 .. (p14).

(53) The selectivity of the second-order bandpass filter is usually measured by its 3-dB bandwidth. This is the difference between the two frequencies ω1 and ω2 ,. ω1 , ω2 = ω0 1 + (1 / 4Q 2 ) ±. ω0 2Q. Thus the bandwidth is going to be BW≡ ω2 - ω1 = ω0/Q Notice that as Q increases, the bandwidth decreases and the bandpass filter becomes more selective. Notch frequency – if the transmission zeros are located on the jωaxis, at the complex conjugate locations ± jωn, then a notch in the magnitude response occurs at ω = ωn , the ωn is known as the notch frequency.. (p15).

(54) Three cases of the second-order notch filter – 1. Regular notch – when ωn = ω0 2. Low-pass notch - when ωn > ω0 3. High-pass notch - when ωn < ω0 Notice that in all notch cases, the transmission at dc and at s = ∞ is finite => there are no transmission zeros at either s = 0 or s = ∞. All-pass filter – the two transmission zeros are in the right half of the s-plane, at the mirror-image locations of the poles. The magnitude response of the all-pass function is constant over all frequencies, the flat gain which is equal to |a2| and so the frequency selectivity of the all-pass function is in its phase response.. Second-Order LCR Resonator Resonator natural modes – the natural modes of a parallel resonance circuit can be determined by applying an excitation that does not change the natural structure of the circuit. Two possible approaches – 1. Exciting with a current source I connected in parallel. 2. Connecting to an ideal voltage source Vi.. (p16).

(55) Taking an example of the form of a voltage divider as shown in the following figure.. The transfer function realized is, T ( s ) =. Vo ( s ) Z 2 (s) = Vi ( s ) Z1 ( s ) + Z 2 ( s ). We observe that the transmission zeros are the values of s at which Z2(s) is zero provided that Z1(s) is NOT simultaneously zero, and the values of s at which Z1(s) is infinite provided that Z2(s) is not simultaneously infinite. ( also see the physical sense in the textbook ! ) Realization of the Low-Pass Function -. (p17).

(56) (p18).

(57) Second-order Active Filters Based on Inductor Replacement The circuits are based on an op amp-RC resonator obtained by replacing the inductor L in the RLC resonator with an op ampRC circuit that has an inductive input impedance.. The input impedance can be shown to be Z in ≡ V1 / I1 = sC4 R1 R3 R5 / R2 which is that of an inductance L given by L = C4 R1 R3 R5 / R2 The analysis of the circuit assuming that the op amps are ideal and thus that a virtual short circuit appears between the two input terminals of each op amp and assuming that the input currents of the op amps are zero. ( shown in the next page ! ) By selecting R1= R2 = R3 = R5= R and C4 = C, we obtain L = CR2.. (p19).

(58) The Op Amp-RC Resonator – We can also replace the inductor L of the RLC resonator we studied in the previous section. The circuit of Fig. 11.21(b) ( see the textbook ) is a second-order resonator having a pole frequency,. ω0 = 1 / LC6 = 1 / C4C6 R1 R3 R5 / R2 and a pole Q factor, Q = ω0C6 R6 = R6. C6 R2 C4 R1 R3 R5. Let C4 = C6 = C and R1 = R2 = R3 = R5 = R obtain. ω0 = 1 / CR Q = R6 / R By selecting C and a given ω0 , we obtain R . With the determined R to realize a given Q, we can determine R6.. (p20).

(59) Realization of the Various Filter Types The op amp-RC resonator can be employed to generate circuit realizations for the various second-order filter functions by following the approach described in the previous section in connection with the RLC resonator. In all cases, the output can be taken as the voltage across the resonance circuit, Vr. However, this is not a convenient node to employ as the filter output terminal since connecting a load would change the filter characteristics. ⇒ The problem can be solved easily by utilizing a buffer amplifier.. (p21).

(60) (p22).

(61) The All-Pass Circuit – An all-pass function with a flat gain of unity can be expressed as AP = 1 – ( BP with a center frequency gain of 2 ) Notice that two circuits whose transfer functions are related in this fashion are called to be complementary. ⇒ Thus the all-pass circuit with unity flat gain is the complement of the bandpass circuit with a center-frequency gain of 2.. (p23).

(62) A simple procedure for obtaining the complement of a given linear circuit : (1). Disconnect all the circuit nodes that are connected to ground and connect them to Vi. (2). Disconnect all the nodes that are connected to Vi and connect them to ground. ⇒ Interchanging input and ground in a linear circuit generates a circuit whose transfer function is the complement of that of the original circuit.. (p24).

(63) Second-order Active Filters Based on the Two-integratorloop Topology The circuits are based on the use of two integrators connected in cascade in an overall feedback loop. The two-integrator-loop biquadratic circuit ( biquad ) can be considered from the second-order high-pass transfer function. Ks 2 = 2 2 Vi s + s (ω0 / Q) + ω0. Vhp. Cross-multiplying and divided both sides by s2 yields 2 ⎞ 1 ⎛ ω0 ⎞ ⎛⎜ ω0 Vhp + ⎜ Vhp ⎟ + ⎜ 2 Vhp ⎟⎟ = KVi Q⎝ s ⎠ ⎝ s ⎠. See the following figure,. −. ω0 s. Vhp. ω0 2 s2. Vhp. How to form Vhp ? We can rearrange the above equation to give, 2 ⎞ 1 ⎛ ω0 ⎞ ⎛⎜ ω0 Vhp = KVi − ⎜ Vhp ⎟ − ⎜ 2 Vhp ⎟⎟ Q⎝ s ⎠ ⎝ s ⎠. which gives a clear message that Vhp can be obtained by using the weighted summer as shown on the top of next page.. (p25).

(64) ω0 2. -1. s2. −. Vhp. ω0 s. Vhp. The complete block-diagram realization is shown in the following figure.. The output of the summer realizes the high-pass transfer function, and the signal at the output of the first integrator is –(ω0/s)Vhp which is a bandpass function,( center frequency gain, -KQ ). (−ω0 / s )Vhp Vi. =. − Kω 0 s = Tbp ( s ) 2 2 s + s (ω0 / Q) + ω0. The signal at the output of the second integrator is a low-pass function,. (ω0 / s 2 )Vhp 2. Vi. Kω 0 = 2 = Tlp ( s ) 2 s + s (ω0 / Q) + ω0 2. Therefore the two-integrator-loop biquad realizes the three basic second-order filtering functions simultaneously, which also called universal active filter.. (p26).

(65) Circuit Implementation – Replace each integrator with a Miller integrator circuit having RC = 1/ω0 . Replace the summer block with an op amp summing circuit that is capable of assigning both positive and negative weights to its inputs. ⇒ KHN biquad.. By employing superposition , we can obtain R3 ⎛ R f ⎜1 + Vhp = R2 + R3 ⎜⎝ R1. ⎞ R2 ⎛ R f ⎞⎛ ω0 ⎞ R ⎟⎟⎜ − Vhp ⎟ − f ⎜⎜1 + ⎟⎟Vi + R2 + R3 ⎝ R1 ⎠⎝ s ⎠ R1 ⎠. ⎛ ω0 2 ⎞ ⎜ 2 Vhp ⎟ ⎜ s ⎟ ⎝ ⎠. Design procedure – 1. Equating the above equation with the last equation on page 25. We obtain Rf/R1 = 1 . ( so we may choose any resistance as long as their ratio is equal to 1 ) 2. Also, from the above approach, we obtain R3/R2 = 2Q – 1. 3. Finally, we also obtain K = 2 – ( 1 / Q ).. (p27).

(66) Notch filtering – Notice that we can realize all-pass functions by summing weighted versions of the three outputs. A notch is obtained by letting RB = ∞ and. RH ⎛ ωn ⎞ = ⎜⎜ ⎟⎟ RL ⎝ ω0 ⎠. 2. An alternative two-integrator-loop biquad circuit in which all three op amps are used in a single-ended mode. Here all the coefficients of the summer have the same sign, and we can dispense with the summing amplifier altogether to carry out the summation at the virtual-ground input of the first integrator as shown in the following figure.. The circuit implementation is shown in the following figure. Note that here the high-pass function is no longer available !. (p28).

(67) Single-Amplifier Biquadratic ( SAB ) Active Filters The fact for the previously introduced op amp-RC biquad circuits is they are NOT economic in their use of op amps – they require three or four amplifiers per second-order section !! In other words, the power dissipation can be a problem. So, here we introduce a class of second-order filter circuits that requires ONLY one op amp per biquad. The synthesis of SABs follows a two-step process(1). Synthesis of a feedback loop that realizes a pair of complex conjugate poles characterized by a frequency ω0 and a Q-factor, Q. (2). Injecting the input signal in a way that realizes the desired transmission zeros.. Synthesis of the Feedback Loop –. The transfer function t(s) can in general be written as the ratio of two polynomials N(s) and D(s) as. t ( s) =. N ( s) D( s). (p29).

(68) The loop gain L(s) of the feedback circuit can be described as L( s ) = At ( s ) =. AN ( s ) D( s). and the characteristic equation of the feedback system is. 1 + L( s ) = 0 since the poles sp of the closed-loop circuit can be obtained as the solutions of the equation, we have t ( s ) = − 1 p A In the ideal case, A = ∞ and the poles are obtained from N(sp)=0. Therefore, the filter ( the feedback system ) poles are identical to the zeros of the RC network. So, how can we synthesize the filter ? Here we know we should select an RC network that has complex conjugate transmission zeros. We may employ bridged-T networks shown in the following figures.. (p30).

(69) The pole polynomial of the active-filter circuit will be equal to the numerator polynomial of the bridged-T network ; thus s2 + s. ⎛ 1 1 ⎞ 1 1 2 + ω0 = s 2 + s⎜⎜ + ⎟⎟ + Q ⎝ C1 C2 ⎠ R3 C1C2 R3 R4. ω0. And ω0 and Q are. 1 ω0 = C1C2 R3 R4. ⎡ CC R R Q=⎢ 1 2 3 4 R3 ⎢⎣. ⎛ 1 1 ⎞⎤ ⎜⎜ + ⎟⎟⎥ ⎝ C1 C2 ⎠⎥⎦. −1. Injecting the Input Signal – Having synthesized a feedback loop that realized a given pair of poles, we now consider connecting the input signal source to the circuit without altering the poles. Remember that put any excitations shall not change the natural structure of the circuit. In addition, depending on the components through which the input signal is injected, different transmission zeros are obtained. Let’s take an example, consider the feedback loop shown in the following figure,. (p31).

(70) Notice that here we have two grounded nodes that can serve for injecting the input signal as shown in the following figure.. Analysis of the circuit to determine its voltage transfer function T(s) ≡Vo(s)/Vi(s) is illustrated in the following figure.. The result is the transfer function Vo = Vi. − s (α / C1 R4 ) ⎛ 1 1 ⎞ 1 1 s 2 + s⎜⎜ + ⎟⎟ + ⎝ C1 C2 ⎠ R3 C1C2 R3 R4. We recognize this as a bandpass function whose center-frequency gain can be controlled by the value of α.. (p32).

(71) Generation of Equivalent Feedback Loops The complementary transformation of feedback loops is based on the property of linear networks illustrated in the following figure.. The transfer function from c to a with b grounded can be shown to be the complement of t, that is 1-t. Application of the complementary transformation to a feedback loop to generate an equivalent feedback loop is a two-step process : (1). Nodes of the feedback network and any of the op amp inputs that are connected to ground should be disconnected from ground and connected to the op amp output. Conversely, those nodes that were connected to the op amp output should be now connected to ground. (2). The two input terminals of the op amp must be interchanged.. Notice that the feedback loop generated by this transformation has the same characteristic equation, and hence the same poles as the original loop.. (p33).

(72) The property can be illustrated by the following example.. If the op amp has an open-loop gain A, the follower will have a gain of A/(A+1) and the transfer function of the network n from c to a is 1-t yields the circuit characteristic equation,. 1−. A (1 − t ) = 0 A +1. That is, 1+At = 0, which is the characteristic equation of the loop in the figure (a). Consider the application of the complementary transformation to the feedback loop shown in the following figure.. (p34).

(73) Let’s take another example shown in the following figure,. The feedback loop realizes a pair of complex conjugate natural modes having the same location as the zeros of t(s) of the RC network. Injecting the input signal to the C4 terminal that is connected to ground can be shown to result in a bandpass realization. However, by employing complementary transformation to fig.(a), we obtain the equivalent loop in fig.(b) which can be used to realize a low-pass function by injecting the input signal as shown in fig.(c).. (p35).

(74) Sensitivity Two obvious facts exist in op-amp design : ( 1 ). The tolerances in component values. ( 2 ). The finite op-amp gain. ⇒ The response of the actual filter will deviate from the ideal response. ⇒ So, we need to employ the concept of sensitivity. In particular, the second-order filters one is usually interested in finding how sensitive their poles are relative to variations in RC component values and amplifier gain. Classical sensitivity function defined,. Δy / y Δx →0 Δx / x. S xy ≡ Lim Thus,. S xy =. ∂y x ∂x y. Here, x denotes the value of a component ( R, C, A,…. ) and y denotes a circuit parameter of interest ( Q,… ). For small changes,. Δy / y S ≅ Δx / x y x. Thus we can use the value to determine the per-unit change in y due to a given per-unit change in x.. (p36).

(75) Switched-Capacitor Filters -. (p37).

(76) Req = 1/ (fc⋅C). (p38).

(77) (p39).

(78) This occupies ≈ (4μm×4μm), rather than (1600μm×1600μm ) for a 10M ohm R. ⇒. (p40).

(79) (p41).

(80) (p42).

(81) (p43).

(82) (p44).

(83) Lecture 4a – Oscillators There are two distinctly different approaches for the generation of sine waves. The first approach employs a positive-feedback loop consisting of an amplifier and an RC or an LC frequencyselective network. The second approach is by appropriately shaping a triangular waveform to obtain sine waves . Linear oscillators – Utilizing resonance phenomena to generate sine waves. Nonlinear oscillators – Circuits that generate square, triangular, pulse…waveforms are called nonlinear oscillators ( function generators ) which employ circuit building blocks known as multivibrators.. Basic Principles of Sinusoidal Oscillators The design techniques can be performed in two steps – (1). A linear and frequency-domain methods of feedback circuit analysis. (2). A nonlinear mechanism for amplitude control.. The Oscillator Feedback Loop The basic structure of a sinusoidal oscillator consists of an amplifier and a frequency-selective network connected in a positive-feedback loop.. (p1).

(84) Here we spot that there is a bit different from the negativefeedback loop as we have seen previously. The feedback signal xf is summed with a positive sign. Thus,. Af (s) =. A( s ) 1 − A( s ) β ( s ). Here we define the loop gain of the circuit is A(s)β(s) thus,. L( s ) ≡ A( s ) β ( s ) The characteristic equation thus becomes 1-L(s) = 0. The Oscillator Criterion – If at a specific frequency f0 the loop gain A(s)β(s) is equal to unity, then Af will be infinite ! ⇒. at this frequency, the circuit will have a finite output for zero input signal.. ⇒. such a circuit is by definition an oscillator.. The condition for the feedback loop to provide sinusoidal oscillations of frequency ω0 is that L( jω0 ) ≡ A( jω0 ) β ( jω0 ) = 1. (p2).

(85) In other words, it implies at ω0 the phase of the loop gain should be zero and the magnitude of the loop gain should be unity. This is known as the Barkhausen criterion. Taking another look for the criterion. Here the relationships between the circuit parameters will be,. x f = β x0 This is, which results in. Ax f = x0 Aβ x0 = x0. Aβ = 1. The frequency of oscillation ω0 is determined solely by the phase characteristics of the feedback loop. The stability of the frequency of oscillation will be determined by the manner in which the phase ϕ(ω) of the feedback loop varies with frequency. A steep function ϕ(ω) will result in a more stable frequency. We may also employ an alternative approach to study oscillator circuits which we can examine the circuit poles. Let’s check the roots of the characteristic equation. For a circuit to produce sustained oscillations at a frequency ω0 the characteristic equation has to have roots at s = ±jω0 . In other words, 1-A(s)β(s) should have a factor of the form s2+ ω02. (p3).

(86) Nonlinear Amplitude Control The Barkhausen criterion guarantees sustained oscillations in a mathematical sense which may need to be revised in physical cases. Obviously, when the temperature changes then Aβ becomes slightly less than unity and of course oscillations will cease. Conversely, oscillations will grow in amplitude. ⇒ We need a mechanism to force Aβ to remain equal to unity at the desired value of output amplitude. ⇒ A nonlinear circuit for gain control. General rule for gain-control mechanism – (1). Ensure oscillations will start by letting Aβ slightly greater than unity. ( the poles are in the right half of the s-plane ) (2). As the power supply is turned on, oscillations will grow in amplitude (3). When the amplitude reaches the desired level, the nonlinear network comes into action and causes the loop gain to be reduced to exactly unity ( the poles pulled back to the jω-axis ) (4). If for some reason, the loop gain is reduced below unity, the amplitude of the sine wave will diminish and this will be detected by the nonlinear network which will cause the loop gain to increase to exactly unity.. (p4).

(87) Two approaches to implement the nonlinear amplitudestabilization mechanism. (1). Limiter circuit. (2). Element whose resistance can be controlled by the amplitude of the output sinusoid. A popular limiter circuit for amplitude control -. The linear operation part of the circuit comprises an inverting amplifier with the relationship. vo = −( R f / R1 )vI. and nonlinear part D1 and D2. Let’s firstly apply a small vI, thus the output vo is also small. Note that by employing superposition we can obtain vA = V. R3 R2 + vo R2 + R3 R2 + R3. vB = −V. R5 R4 + vo R4 + R5 R4 + R5. (p5).

(88) . Obviously, D1 and D2 must be off. As vI goes positive, vo goes negative , vB will become more negative, thus keeping D2 off. However, vA becomes less positive. Continue to increase vI, a negative value of vo will be reached at which vA becomes –0.7V and D1 conducts.. . Notice that at this point, we reach the negative limiting level, which denotes L_, ( here we use constant-voltage-drop model for D1 ). . L _ = −V. R3 R − VD (1 + 3 ) R2 R2. If vI is increased beyond this value, more current is injected into D1 and vA remains at approximately –VD. ⇒ The current through R2 remains constant and the additional diode current flows through R3. ⇒ R3 appears in effect in parallel with Rf , and the incremental gain is –(Rf // R3)/R1. ⇒ So how to choose the value of R3 ?. . The transfer characteristic for negative vI can be found in a manner identical to that employed above.. . Increasing Rf results in a higher gain in the linear region while keeping L_ and L+ unchanged. In other words, when Rf is removed the limiter turns into a comparator.. (p6).

(89) OP Amp-RC Oscillator Circuits The Wien-Bridge Oscillator The circuit consists of an op-amp connected in the noninverting configuration with a closed-loop gain of 1 + R2/R1. The loop gain is. Thus. L( s ) =. ⎡ R ⎤ Zp L( s ) = ⎢1 + 2 ⎥ ⎣ R1 ⎦ Z p + Z s. 1 + R2 / R1 1 + R2 / R1 = 3 + sCR + 1 / sCR 3 + j (ωCR − 1 / ωCR ) s = jω. The loop gain shall be a real number at one frequency given by 1 ω0CR = That is, ω0 = 1 / CR ω0CR To obtain sustained oscillations at this frequency, the magnitude of the loop gain should be set unity by selecting R2 / R1 = 2 Moreover, the amplitude of oscillation can be determined and stabilized by using a nonlinear control network as shown in the next page.. (p7).

(90) Here the limiter circuit consists of D1, D2, R3, R4, R5, R6. Alternatively, one can use the following implementation.. (p8).

(91) The Phase-Shift Oscillator The basic structure of the phase-shift oscillator is shown in the following figure which consists of a negative-gain amplifier ( -K ) with a threesection RC ladder network in the feedback.. The circuit will oscillate at the frequency for which the phase shift of the RC network is 180o. Why use three instead of two…..? ( recall that the transfer function of a high-pass model, not possible to obtain 90o for each stage ) Notice that for oscillations to be sustained, the value of K shall be equal to the inverse of the magnitude of the RC network transfer function at the frequency of oscillation. The Quadrature Oscillator Based on the two-integrator loop as we have mentioned previously. Ensure to locate the poles on the jω-axis in order to provide sustained oscillations. However, we initially located in the right half-plane and then pulled back by the nonlinear gain control.. (p9).

(92) Amplifier 1 connected as an inverting Miller integrator with a limiter in the feedback for amplifier control. Amplifier 2 is connected as a non-inverting integrator. Let’s further investigate the circuit behaviour – By replacing vo1 and 2R with its Norton equivalent circuit, we obtain the circuit shown in figure (b), in which we spot that vo2 =2v and the current through Rf will be ( 2v – v )/Rf = v/Rf in the direction from output to input, thus Rf gives rise to a NEGATIVE input resistance, -Rf which is made equal to 2R ⇒ -Rf cancels 2R. ⇒ a current source vo1/2R feeding a capacitor. ⇒ a perfect non-inverting integrator. The loop gain. L( s ) ≡. Oscillation frequency. Vo 2 1 =− 2 2 2 Vx sC R. ω0 =. 1 CR. (p10).

(93) Since vo2 is the integral of vo1, the two output signal shall have 90o phase difference. The Active-Filter Tuned Oscillator The approach can result in high-quality output sine waves. Let’s take a look at the following figure,. The circuit consists of a high-Q bandpass filter connected in a positive-feedback loop with a hard-limiter. The sine-wave signal v1 is fed to the limiter, which produces at its output a square wave whose levels are determined by the limiting levels and whose frequency is f0. Obviously, the purity of the output sine wave will be a direct function of the selectivity of the bandpass filter. One possible implementation is shown in the following figure, which the circuit uses a variation on the bandpass circuit based on the Antoniou inductance-simulation circuit.. (p11).

(94) LC Tuned Oscillators –. vin. +. Σ. G(jω). vout. + H(jω). . The figure above shows the necessary components of an oscillator. It contains an amplifier with frequency-dependent forward loop gain G(jω) and a frequency-dependent feedback network H(jω). The output voltage is thus given by. Vo =. VinG ( jω ) 1 − G ( jω ) H ( jω ). For an oscillator, the output V0 is nonzero even if the input signal Vi = 0. This can only be possible if (I). The forward loop gain is infinite. (II). The denominator 1- G(jω)H(jω) = 0 at some frequency ω0 ⇒ Nyquist criterion ( G(jω0)H(jω0) = 1 ). (p12).

(95) In other words, two conditions shall be satisfied, ‘the magnitude of the open-loop transfer function is equal to 1 (|G(jω0)H(jω0)|= 1) and the phase shift is 00 ‘ Circuit Implementations –. hie. Z3. Z1. Vin. Z2. βib. hoe. ZL. The figure above shows a generalized circuit for an electronic amplifier. If hoe is assumed sufficiently small and can be neglected. The loop equations are then Vin =I1 ( Z3 + Z1 + Z2 ) – IbZ1 + βIbZ2 0 = -I1Z1 + Ib ( hie + Z1 ). For the amplifier to oscillate, the system determinant is equal to 0, ( Z3 + Z1 + Z2 ) ( hie + Z1 ) - Z12 + β Z1Z2 = 0. that is,. which yields ( Z3 + Z1 + Z2 ) hie + Z1Z2 β + Z1 ( Z3 + Z2 ) = 0 Therefore, and. ( Z3 + Z1 + Z2 ) hie = 0, and Z1[(1+ β ) Z2 + Z3 ] = 0. (1+ β ) Z2 = -Z3 , thus Z1 + Z2 - (1+ β ) Z2 = 0. or. Z1 = β Z2. Since β is positive, Z1 and Z2 will be reactance of the same type. ⇒ If Z1 and Z2 are capacitors, Z3 is an inductor, the circuit is Colpitts oscillator. ⇒ If Z1 and Z2 are inductors, Z3 is a capacitor, the circuit is Hartley oscillator. (p13).

(96) The following circuits illustrate the two configurations,. In both circuits, the resistor R represents the losses of the inductors, the load resistance of the oscillator, and the output resistance of the transistor. The frequency of oscillation will be determined by the resonance frequency of the parallel-tuned circuit ( known as a tank circuit since it behaves as a reservoir for energy storage ). Thus, the resonance frequency for Colpitts oscillator will be, ⎛ CC. ⎞. ω0 = 1 / L⎜⎜ 1 2 ⎟⎟ ⎝ C1 + C2 ⎠ and. ω0 = 1 / C ( L1 + L2 ). for Hartley oscillator.. Note that C1 / C2 or L1 / L2 determines the feedback factor and thus must be adjusted in conjunction with the transistor gain to ensure that oscillations will start. The analysis can be referred to the following equivalent circuit.. (p14).

(97) To find the loop gain, we break the loop at the transistor base, apply an input voltage Vπ and find the returned voltage that appears across the input terminals of the transistor. Analyzing the node equation of node C yields. ⎛ 1 ω 2 LC2 ⎞ ⎟⎟ + j ω (C1 + C2 ) − ω 3 LC1C2 = 0 ⎜⎜ g m + − R R ⎠ ⎝. [. ]. So, what’s the next step ?. Crystal Oscillators – A piezoelectric crystal ( such as quartz ) exhibits electromechanicalresonance characteristics that are very stable ( in terms of time and temperature ) and highly selective ( high Q factors ) The circuit symbol of a crystal is shown in the following figure.. (p15).

(98) Notice that here we have a large inductance L ( hundreds of henrys ), a very small series capacitance Cs , a series resistance r representing a Q factor that can be as high as a few hundred thousand, and a parallel capacitance Cp. ( Cp >> Cs ) The crystal impedance can be represented as ⎡ ⎤ 1 Z ( s ) = 1 / ⎢ sC p + ⎥ sL + 1 / sCs ⎦ ⎣ In addition, we see that the crystal has two resonance frequencies :. ω s = 1 / LC s and a parallel resonance frequency. ⎛ CC. ⎞. ω p = 1 L⎜⎜ s p ⎟⎟ ⎝ Cs + C p ⎠. We can rewrite the crystal impedance as. 1 Z ( jω ) = − j ωC p. ⎛ ω 2 − ωs 2 ⎞ ⎜ ⎟ 2 2 ⎜ω −ω ⎟ p ⎠ ⎝. We also know that ωp > ωs and Cp >> Cs , thus the two resonance frequencies are very close. Expressing Z(jω) = jX(ω), the crystal reactance X(ω) will have the shape shown in fig.(c), which is inductive over the very narrow frequency band between ωs and ωp. Note that the reactance is inductive, we may replace the inductor of the Colpitts oscillator with the crystal and the resulting parallel capacitance CC is Cp + 1 2 C1 + C2 Since Cs is much smaller than the resulting parallel capacitance, it will dominant and the resonance frequency is. ω0 ≈ 1 / LC s = ωs. (p16).

(99) Other popular configuration using crystal like Pierce oscillator is shown in the following figure which employs a CMOS inverter as the amplifier.. Resistor Rf determines a dc operating point in the high-gain region of the CMOS inverter. Resistor R1 and capacitor C1 provide a low-pass. filtering. function. which. depresses the higher harmonics of the crystal frequency. Crystals are available with resonance frequencies in the range of few kHz to hundreds of MHz and the temperature coefficients of. ω0 of 1 or 2 ppm ( parts per million ) per oC are available. However, due to being mechanical resonators, crystal oscillators are fixed-frequency circuits.. (p17).

(100) Lecture 4b – Multivibrators Bistable multivibrator – has two stable states ; the circuit can remain in either stable state indefinitely and moves to the other stable state ONLY when appropriately triggered.. The Feedback Loop – Bistability can be obtained by connecting an amplifier in a positive-feedback loop having a loop gain greater than unity as shown in the following figure which consists of an op-amp and a resistive voltage divider in the positive-feedback loop.. Assume the electrical noise that is inevitably present which causes a small positive increment in the voltage v+. The incremental signal will be amplified by the large open-loop gain A of the op amp resulting in much greater signal in the opamp’s output voltage vo. Notice that the feedback factor β = R1/(R1+R2) which feed the fraction of the output signal back to the positive input terminal of the op amp. If loop gain βA is greater than unity, the fed-back signal will be greater than the original increment in v+.. (p1).

(101) The regenerative process continues until eventually the op amp saturates with its output voltage at the positive saturation level, L+ The voltage at the positive input terminal becomes L+R1/(R1+R2) which is positive and thus keeps the op amp in positive saturation. So, what’s happening for a negative increment ? We thus conclude the circuit has two stable states, one with the op amp in positive saturation and the other with the op amp in negative saturation.. Transfer Characteristics of the Bistable Circuit – Refer to the circuit we know that there are two circuit nodes that are connected to ground can serve as an input terminal. One possible external input configuration is shown in the follows,. (p2).

(102) Here an input vI applied to the inverting input terminal of the op amp. As vI is increased from 0V there is nothing happens until vI reaches a value equal to v+ ( βL+, L+ is one of the two possible levels ) As vI begins to exceed this value, a NET negative voltage develops between the input terminals of the op amp and this voltage is amplified by the open-loop gain of the op amp which makes vo goes negative. Finally, the voltage divider in turn causes v+ to go negative, thus increasing the net negative input to the op amp and keeping the regenerative process going. Let’s consider what happens as vI is decreased. Here we see that the circuit remains in the negative-saturation state until vI goes negative to the point that it equals βL-……... (p3).

(103) As vI goes below this value,……. The complete transfer characteristics indicates the circuit changes state at different values of vI , depending upon whether vI is increasing or decreasing ⇒ hysteresis. The width of the hysteresis is the difference between the high threshold VTH and the low threshold VTL. Since the bistable circuit switches from the positive state to negative state as vI is increased past the positive threshold VTH, the circuit is said to be inverting.. Triggering the Bistable Circuit – According to the last figure, we know that if the circuit is in the L+ state it can be switched to the L- state by applying an input vI of value greater than VTH ≡ βL+. Such an input causes a net negative voltage to appear between the input terminals of the op amp, which initiates the regenerative cycle that culminates in the circuit switching to the L- stable state. The input signal vI is thus referred to as a trigger signal ( trigger ).. The Bistable Circuit as a Memory Element – Notice that for input voltages in the range VTL < vI < VTH the output can be either L+ or L- , depending on the state that the circuit is already in.. (p4).

(104) Thus for this input range, the output is determined by the previous value of the trigger signal. ⇒ The circuit exhibits memory. Note that we also call the bistable circuit as a Schmitt trigger.. A Bistable Circuit with Non-inverting Transfer Characteristics – By applying a trigger signal vI to the terminal of R1, we can obtain a bistable circuit with non-inverting transfer characteristics.. By employing superposition, we can express v+ in terms of vI and vo as. v+ = v I. R2 R1 + vO R1 + R2 R1 + R2. Here we know for positive stable state vo = L+ , positive values vI make v+ remain in positive values. However, for negative vI we can trigger the circuit into the Lstate by letting v+ decrease below zero. Thus, the low threshold VTL can be obtained by substituting v0 = L+ , v+ = 0 and vI = VTL into the above equation, which results in. VTL = − L+ ( R1 / R2 ). (p5).

(105) . So, what’s going to happen for VTH ?. The Bistable Circuit as a Comparator – . Recall that we use comparators in some analog-circuit building blocks such as in analog-to-digital ( A/D ) converters. Note that we may think comparators have only a single threshold value as shown in the following figures.. . However, it can be very useful to add hysteresis to a comparator in many applications. In other words, we obtain TWO threshold values, VTL and VTH symmetrically placed around the desired reference level as shown in figure (b).. (p6).

(106) Let’s see what happen if we got interference in a circuit as shown in the following figure.. The signal might cross the zero axis a number of times around each of the zero-crossing points. The comparator would thus change state a number of times at each of the zero crossings, which it can lead to malfunctions. However, if we have an idea of the expected peak-to-peak amplitude of the interference, the problem can be solved by introducing hysteresis of appropriate width in the comparator characteristics. In other words, if the input signal is increasing in magnitude, the comparator with hysteresis will remain in the low state until the input level exceeds the high threshold VTH and vice versa.. (p7).

(107) We can also employ limiter circuits to obtain more precise output levels as illustrated in the following figures.. Generation of Square Waveforms using Astable Multivibrators A square waveform can be generated by arranging for a bistable multivibrator to switch states periodically, which we can connect the bistable multivibrator with an RC circuit in a feedback loop as shown in the following figure.. (p8).

(108) Operation of the Astable Multivibrator Let’s firstly investigate the operation of the following circuit. Since we obtain a positive feedback configuration, we may assume the output of the bistable multivibrator be one of the possible levels, say L+.. Capacitor C will start to charge toward this level through resistor R. Thus the voltage at v- will rise exponentially toward L+ with a time constant τ = CR and the voltage at v+ = βL+. This situation will continue until the capacitor voltage reaches the positive threshold VTH at which point the bistable multivibrator will switch to the other stable state in which vo = L- and v+ = βL-. And then the capacitor starts to discharge, and its voltage v- will decrease exponentially toward L-. By this brief investigation, we realize the astable circuit oscillates and produces a square waveform at the output of the op amp. But, how can we find out the period T of the square wave ? ( Recall the time constant RC ……. ). (p9).

(109) We may simplify the circuit as an RC circuit as shown in the following. L- ( or L+ ). Case 1 : ( when vo = L- we calculate T2 ) v- will be from βL+ to βLRecall that v − = L − + ke force response. and. −. t RC. βL+ = L− + k ⇒ k = βL+ − L−. natural response. v− (t) = L− + (ββ + − L− )e. ⇒ T2 = τ ln. thus. 1 − β ( L+ / L− ) 1− β. −. t RC. Therefore, β L− = L− + ( β L+ − L− )e. v− = L+ + ke. −. t RC. and βL− = L+ + k ⇒ k = β L− − L+ Therefore, β L+ = L+ + ( β L− − L+ )e. 1 − β ( L− / L+ ) 1− β. T2 RC. where τ = RC. Nevertheless, T1 can be calculated from. ⇒ T1 = τ ln. −. ⇒ T = T1 + T2 = 2τ ln. 1+ β 1− β. −. T1 RC. (p10).

(110) Note that here we also call the astable circuit has two quasi-stable states.. Generation of Triangular Waveforms – We can obtain triangular waveforms by replacing the low-pass RC with an integrator as shown in the following figures.. The basic idea is that the integrator causes LINEAR charging / discharging of the capacitor, which provides a triangular waveform.. (p11).