具場引效汲極的蕭特基能障薄膜電晶體 之研製與特性分析
研 究 生 : 葉 冠 麟 指導教授 : 黃調元 博士 林鴻志 博士
國立交通大學電子工程學系電子研究所 摘要
蕭特基能障金氧半場效電晶體擁有較簡單且適用於低溫的製程。它同時也具 有雙極性操作與短通道效應控制力。然而，嚴重的漏電流是它的缺點。如果該缺 點能夠改善，則蕭特基能障金氧半場效電晶體的雙極性操作特性將使其製程與電 路設計更具彈性。如果這種構想能夠用在薄膜電晶體，則蕭特基薄膜電晶體的低 製程溫度與金屬化接面將使此一元件非常適用於主動式陣列液晶顯示器之製 造。此外，金屬矽化物製程不但可以降低熱預算，亦可減少源極/汲極的寄生電 阻。
在本論文中，我們成功的研發出一種新式具有金屬矽化物源極/汲極與場引 效汲極的蕭特基能障薄膜電晶體。該結構在鈍化氧化層有一金屬 field-plate(或稱 為副閘極)，對其施以固定偏壓，以在金屬矽化汲極與元件主通道間引伸出一層 載子作為補償通道。經由副閘極偏壓極性的轉換，則該元件即可展現雙極性操作 特性。相較於傳統結構的蕭特基能障薄膜電晶體在關閉狀態時展現嚴重的閘極引 致汲極漏電流，我們的新結構可以成功的將該漏電流抑制住。進而在 p-型與 n-
型元件操作下提高開關電流比達 106。更甚者，因為不用離子佈植，與雙極性的
展現，使得該製程能在極少的光罩數下就完成 CMOS 製程。上述特性使該元件 特別適用於大面積的電子產品應用。
接著，我們利用實驗上的方式去分別分析傳統與新式元件的漏電流機制。結 果顯示傳統元件的漏電流的活化能隨汲極和主閘極壓差的增加而下降。這暗示在 汲極區的場發射隨電場增強而增強，並使類似 GIDL 的現象更強。相對的，具場 引效汲極結構的元件的漏電活化能就和汲極和主閘極壓差的相關性甚低。因為其 費米能階會因高副閘極電壓而靠近導電或價電帶，而使高電場區遠離汲極接面。
所以熱離子發射將主導關閉狀態的漏電機制，進而抑制類似 GIDL 的漏電流。
為大幅提高元件特性，我們將準分子雷射結晶技術應用於元件上。因為薄膜
特性之改善，開關電流比可提升至 108。我們發現對具有較高能障的 n-型元件而
言，源極的載子穿透效應比熱離子發射佔有較重要的比重。以其優越的開關特性
i
和簡單化製程，使致這種新式結構確實適用於 AMLCD 和 SOP 應用。
在今日奈米等級元件的研製已是非常普及。我們發現蕭特基薄膜電晶體的特 性可因縮減元件寬度至奈米等級而更獲改善。我們的結果顯示，儘管在 620℃直 接沉積的複晶矽擁有高度的缺陷密度，元件仍能展現高開關電流比與低次臨限擺 幅。顯然若將諸如準分子雷射結晶技術應運於複晶矽薄膜上，則類似 SOI 的元件 表現將是很可以預期的。
最後，我們開發出一種可量得薄膜電晶體通道層之全能障內缺陷態位密度的 新穎方法。在這種方法中，我們以場效應電導法的原理來求取態位密度。微分法 與溫度法分別用以在蕭特基薄膜電晶體和傳統的離子佈植薄膜電晶體上。我們發 現在同樣的通道材料上，不同的元件結構與方式都可以獲得良好的相似結果。這 證明了這種新方式的可行性與可靠度。我們也分析了量測結果與元件結構的相依 性，以獲適當的量測條件。我們發現只要有寄生電阻的出現，就容易高估缺陷密 度的結果。若加以足夠高的汲極電壓，副閘極偏壓或較短的通道都可以減緩上述 現象。此外，採用靠近能障中間的金屬矽化物材質如矽化鈷，將有助於分析的可 靠性。
我們也分析了諸如再結晶法與電漿處理等製程步驟對缺陷態位密度的影 響。使用這種新方法可完整真實反映出該製程的效應。而前述提及的具奈米級寬 度通道的電晶體之良好閘極控制力亦可由缺陷密度之分析來獲得合理解釋。最 後，我們證實元件的平帶電壓可由 p-型與 n-型元件之電流-閘極電壓特性圖曲線 的交點來求得。這樣大大提昇了流程的簡單性，並且，從業界觀點而言可大幅降 低成本，因為只要單一顆元件與室溫下的兩條特性曲線即可求出缺陷態位密度，
其實用性不可言喻。
ii
The Fabrication and Characterization of Schttoky Barrier Thin Film Transistor with Field-Induced-Drain
Student : Kuan-Lin Yeh Advisors: Dr. Tiao-Yuan Huang Advisors: :Dr. Hrong-Chih Lin
Department of Electronics Engineering & Insitute of Electronics National Chiao Tung University
Abstract
Schottky Barrier MOSFET is simpler in processing and inherently suitable for low temperature processing. It is also capable of ambipolar operation and short channel control.
However, it suffers from deleterious off-state leakage current. If the shortcomings of SB-MOSFET could be improved, the inherent ambipolar property of SB-MOSFET will make fabrication process and circuit design more flexible. If the idea is applied to thin film transistors, the low process temperature of metallic junction formation will make SB-TFT compatible with middle temperature active matrix liquid crystal display (AMLCD) manufacture. In addition, salicidation process will not only reduce the thermal budget, but also decrease the source/drain parasitic resistance. This is quite appropriate for low temperature poly-Si application.
In this dissertation, a novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension was proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying over the passivation oxide is employed to induce a sheet of carriers in a channel offset
iii
region located between the silicided drain and the active channel region underneath the main-gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from the low on/off current ratio, the new device exhibits high on/off current ratio of up to 106 for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS processes integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications.
Second, we have experimentally investigated the conduction mechanisms of the off-state leakage current for Schottky Barrier TFTs with FID and conventional structure. The results show that the activation energy of the off-state leakage decreases significantly with increasing
VGD for SBTFT with conventional structure. This indicates that field-emission conduction plays a major role as the field strength in the drain junction becomes high, and results in the strong GIDL-like phenomenon. In contrast, the activation energy of the off-state leakage shows only minor dependence on VGD for SBTFT with FID. This is ascribed to the fact that the high-field region can be pulled away from the silicided drain for the FID structure. As a result, the field-emission conduction will be eliminated, and thus the GIDL-like leakage current can be effectively suppressed.
Next, SBTFT devices with ELA poly-Si active channel were successfully fabricated.
Excellent device performance in terms of steep subthreshold slope and high on/off current
iv
higher than 108 for both p- and n-channel operations are demonstrated, for the first time, on a single poly-Si TFT device. Source-side tunneling process is found to be important for device operation, especially for the n-channel operation that has a larger barrier height. The stellar performance with on/off current ratio larger than 108 for both n- and p-channel modes of operation, together with its inherent ambipolar capability, implantless process, silicided source/drain, low thermal budget, and simplified CMOS integration scheme, makes this kind of device a promising candidate for future AMLCD and SOP applications.
Applications of nano-scale device are very popular nowadays. We will show that the ambipolar performance of SB poly-Si TFTs can be improved by scaling the channel width into the nano-scale regime. Our results indicate that, despite the high trap density in poly-Si films, high on/off current ratio and small subthrehold swing can be achieved. It appears therefore possible to achieve SOI-like device characteristics if poly-Si film improvement methods, such as excimer laser annealing and metal-induced crystallization scheme, are adopted.
Finally, we proposed and successfully demonstrated a novel approach to obtain the full band-gap DOS in the channel of TFT devices. In this approach, the field-effect conductance method is performed on an SB poily-Si TFT which has the capability of ambipolar operation.
Both incremental and temperature methods are adopted on the SB and conventional implanted devices to construct the relationship between DOS and the energy level in the gap. For devices with the same channel material, the results are in good agreement among the different extraction schemes, indicating the novel approach is very reliable.
We have also characterized the dependence of both electrical and structural parameters on the measurement results in order to set suitable test conditions. Our results indicate that the
v
parasitic resistance presenting in the channel would result in the overestimation of tail state density. A sufficiently high drain and sub-gate biases and short electrical junction length are thus needed. In addition, for reliable full band-gap DOS analysis, near-mid-gap silicide material like CoSi2 is desirable.
In addition, the effect of process treatment like the re-crystallization and plasma hydrogenation steps on the DOS characteristics has also been characterized. Their impacts are clearly identified using the new approach. Benefits of using a nano-scale fin channel for promotion of the controllability of gate voltage over the channel potential is also clearly demonstrated.
Finally, we show that the flat-band voltage could be obtained by simply measuring the gate voltage at the intersection point of p- and n-mode I-V curves. The overall process is thus greatly simplified and cost-saving comparing to conventional approach, since only one device and two I-V measurements performed at room temperature are needed. We strongly believe that the novel method is extremely useful for practical applications.
vi
誌 謝
首先向指導教授黃調元博士與林鴻志博士致上無限的謝意，在他們兩人細 心的指導下，本論文得以順利完成。黃老師的廣博多聞使我獲益良多，幽默風趣 的言談使人如沐春風，淡泊寧靜的態度令人敬仰。林博士則是生命中的恩人，在 他的鼓勵與督導下，讓我對做學術的態度有了明瞭，也看到了追求真理的崇高一 面，更讓我的專業知識得以成長，在他的教誨下，使我在學問上有豐足的收穫，
在此實難將心中的謝意表達於萬一。
由衷的感謝林敬偉學長。感謝他在我研究生涯中最徬徨無助的時刻扶了我 一把，並給予我知識上與實驗上的實際協助。他毫不藏思的開闊胸襟與卓越的學 識，令人無比欽佩。感謝王夢凡學長對我的啟蒙訓練，給了我足夠的實驗知識與 技巧，讓我日後得以獨立操作，順利解決問題。感謝盧文泰學長、李達元學長、
鄭仁鈞學長在軟體使用與量測儀器上的教學，感謝楊明瑞、陳宏瑋、陳啟群、俞 正明學長所給予的鼓勵。特別感謝曾經一起共事的學弟蔡仁威、李明賢、林文傑、
李維蘇育正、房新原。是他們使我明白團隊合作的重要性，也謝謝他們在實驗與 量測上的幫忙。感謝同學李耀仁、陳志遠的鼓勵，也感謝學弟呂嘉裕、林宏年、
陳國華、蔡旻育、黃若谷、歐士傑、蘇俊榮、盧景森、林柏青等人在這段歲月裡 的協助。
感謝 NDL 的簡昭欣博士、張茂男博士的指導，與劉正財、侯福居、巫政榮、
謝錦龍、沈士文先生及彭馨誼、范瑞雲、李春杏、陳綉芝、謝竹枝、周家如、蔣 秋芬、趙子綾小姐在技術上的協助，使實驗得以順利完成。
感念大學時代的恩師吳耀華老師，是他的真誠教學喚醒了原本態度懶散的 我，進而鼓勵我向上發展，吳老師對我的恩情猶如再造父母，畢生難忘。另外也 要謝謝好友姚啟順、林威伯、林宣佐、黃逸傑、李崇德、林敬軒、詹宜陵等人的 支持與打氣。感謝統寶光電的林孝義經理及同仁陳維成的關懷及協助，於公於私 給了我很大的方便及空間，展現了業界中溫情的一面。
最後僅將論文獻給我的父母—葉忠國先生與崔麗辰女士，感謝他們三十年 來的養育之恩，辛苦的扶養我長大順利求學，進而有成。在年事稍長，懂得父母 辛勞後，心中的謝意很難用三言兩語表述出來。也感謝我的啟蒙老師—二舅崔元 平先生，在他的帶領下，使我走上唸書的路子。感謝五叔葉裕國先生於這段歲月 裡在交大對我生活上的照顧。由衷地感謝女友高詩涵女士，在我飽受眼疾之苦時 的幫助與鼓勵，恩德永難忘懷。
最後感謝所有幫助過我的朋友及長輩，在這一趟學習之旅中讓我學會了謙 虛，也使我明瞭自己的才能有限，收穫之豐，終生受用。
vii
Contents
Abstract ( Chinese ) i
Abstract ( English ) iii
Acknowledgments ( Chinese ) vii
Contents viii
Figure Captions xii
Table Captions xx
List of Symbols xxi
1 Introduction
………..………...1
1.1 General Background
………...………1
1.1.1 Schottky Barrier MOSFET
………...1
1.1.2 Overview of Thin-Film Transistor
………...2
1.1.3 Development of SOI FinFETs
………6
1.2 Motivation of This Study
………7
1.3 Organization of the Thesis
……….8
2 General Fabrication, Operation and Characteristics of Ambipolar Schottky-Barrier Thin-Film Transistors (SBTFT)
……...………18
2.1 Introduction
………18
2.2 Device Fabrication and Structures
………...19
2.3 Operation of SBTFT with Field-Induced Drain
………20
2.4 Results and Discussion
……….20
2.4.1 Characteristics of Ambipolar Operation
………20
2.4.2 Leakage Mechanisms
………..…….….21
viii
2.4.3 Effects of FID Length
………...22
2.5 Summary
………..24
3 Leakage Current Mechanisms of Schottky Barrier Thin-Film Transistors 3.1 Introduction
………40
3.2 Experiment and Measurement Results
……….40
3.3 Experimental Results
………41
3.4 Leakage Mechanisms
………42
3.5 Summary
………..43
4 Characteristics of SBTFTs with ELC Channel
……….………59
4.1 Introduction
………59
4.2 Device Structure and Fabrication
………..59
4.3 Characteristics of SB-TFTs with ELC Channel
………...60
4.3.1 Transfer Characteristics of ELC and SPC Samples
………..60
4.3.2 Effects of Sub-Gate Bias
………..60
4.3.3 Effects of Main-Channel Length
………63
4.3.4 Effects of Channel Offset Length
………...63
4.4 Off-State Leakage Conduction Mechanisms
………..….64
4.4.1 Devices with Excimer-Laser-Annealed (ELA) Channel
………...64
4.4.2 Devices with Solid-Phase-Crystallized (SPC) Channel
……….65
4.5 Summary
………..66
ix
5 Schottky Barrier TFTs with Nano-Scale Channel Width
………...91
5.1 Introduction
………...91
5.2 Device Fabrication
………92
5.3 Results and Discussion
………..…93
5.4 Summary
………..94
6 A Novel Method to Analyze Full Band-Gap Density of States (DOS) Distribution in Thin Film Transistors
………...110
6.1 Introduction
………..110
6.2 Realization of Full Band-Gap DOS Analysis Using a Single Device
...111
6.2.1 Field Effect Conductance Method
………...111
6.2.2 Operation of Ambipolar TFT
………114
6.3 Analysis of Full Band-Gap DOS in FID-SBTFT Structure
…………...115
6.3.1 Determination of DOS Using Temperature and Incremental Methods
………..115
6.3.2 Effects of Applied Drain Bias
………116
6.3.3 Effects of Channel Length
……….………..117
6.3.4 Effects of Drain-side Extension Length
…...………..…...117
6.3.5 Effects of Measurement Temperature
…..………....118
6.3.6 Results Comparison with Conventional Approach
………..118
x
6.3.7 Effects of Channel Crystallization Treatment
………....118
6.3.8 Effects of Plasma Hydrogenation
…...………...119
6.3.9 Effects of Silicide Material
………...………...119
6.3.10 Analysis of Full Band-Gap DOS in SB Poly-Si FinFET
……....120
6.3.11 A New & Simpler Methodology to Determine Flat-Band Voltage
………..………..121
6.4 Summary
………122
7 Conclusions and Future Works
………..166
7.1 Conclusions
………...166
7.2 Future Works
………169 Vita
Publication List
xi
Figure Captions
Chapter 2
Fig. 2.1 Key fabrication steps for SBTFT devices with (a) conventional and (b) the new structure with field-induced drain (FID). XD in (b) is the length of FID region in the channel.
Fig. 2.2 Ambipolar subthreshold characteristics of a FID SBTFT. VD is 5 and –5 V for n- and p-channel operations, respectively.
Fig. 2.3 Typical p- (Vd = -5V) and n-channel (VD = 5V) subthreshold characteristics of SBTFT with (a) conventional and (b) FID structure. L/W = 2/20 µm/µm.
XD in (b) is 5 µm.
Fig. 2.4 Typical p- and n-channel output characteristics of SBTFT with (a)&(b) conventional and (c)&(d) FID structure. L/W = 2/20 µm/µm. XD in (c) and (d) is 1 µm.
Fig. 2.5 Band diagrams for n-channel operation of SBTFTs with (a) conventional structure, and (b) FID at off-state (i.e., VG, main = 0, VD = VDD, and VG, sub >>
0).
Fig. 2.6 Typical n-channel (Vd = 1V) subthreshold characteristics of SBTFT devices with various XD (e.g., 1, 5, and 10 µm). L/W = 5/20 µm/µm.
Fig. 2.7 Typical p-channel (Vd = -1V) subthreshold characteristics of SBTFT devices with various XD (e.g., 1, 5, and 10 µm). L/W = 5/20 µm/µm.
Fig. 2.8 Effects of the sub-gate bias and XD on the n-channel operation of FID SBTFTs. L/W =5/20 µm/µm.
Fig. 2.9 Effects of the sub-gate bias and XD on the p-channel operation of FID SBTFTs. L/W =5/20 µm/µm.
Fig. 2.10 Vth extracted from the “on” state I-V curves of Figs. 8 and 9 as a function of
xii
XD.
Fig. 2.11 Ratio between the “on” and “off ” state currents (Figs. 8 & 9) for (a) n- and (b) p-channel operations.
Fig. 2.12 Band diagrams for p-channel operation (VD= -3 V) of FID SBTFT with a high positive sub-gate bias.
Chapter 3
Fig. 3.1 Cross-sectional views of SBTFT devices (a) with and (b) without the field plate. XD in (a) is the length of the offset region in the channel.
Fig. 3.2 ID-VG characteristics for n-channel operation of a SBTFT with conventional structure: (a) VD=1V; (b) VD=3V. Channel length and width are 5 and 20 µm, respectively.
Fig. 3.3 ID-VG characteristics for p-channel operation of a SBTFT with conventional structure: (a) VD=-1V; (b) VD=-3V. Channel length and width are 5 and 20 µm, respectively.
Fig. 3.4 Arrhenius plots for n-channel operation of a SBTFT with conventional structure.
Fig.3.5 Arrhenius plots for p-channel operation of a SBTFT with conventional structure.
Fig. 3.6 EA as a function VG for n- and p-channel operations of a SBTFT with conventional structure.
Fig. 3.7 ID-VG characteristics for n-channel operation of a SBTFT with FID structure:
(a) VD=1V; (b) VD=3V. Channel length and width are 5 and 20 µm, respectively. XD is 4µm.
Fig. 3.8 ID-VG characteristics for p-channel operation of a SBTFT with FID structure:
(a) VD=-1V; (b) VD=-3V. Channel length and width are 5 and 20 µm,
xiii
respectively. XD is 4µm.
Fig. 3.9 Arrhenius plots for n-channel operation of a SBTFT with FID structure.
Fig. 3.10 Arrhenius plots for p-channel operation of a SBTFT with FID structure.
Fig. 3.11 EA as a function VG of a SBTFT with FID structure for n- ( top figure ) and p-channel ( bottom figure ) operations.
Fig. 3.12 Band diagram for off-state n-channel operation of SBTFT with conventional structure.
Fig. 3.13 Band diagram for off-state n-channel operation of SBTFT with FID structure.
Chapter 4
Fig. 4.1 Cross section of FID SBTFT.
Fig. 4.2 Ambipolar transfer characteristics of FID SBTFT with ELA channel.
Fig. 4.3 Ambipolar transfer characteristics of FID SBTFT with SPC channel.
Fig. 4.4 Effects of sub-gate bias on p-channel operation of FID SBTFT with ELA channel.
Fig. 4.5 Effects of sub-gate bias on n-channel operation of FID SBTFT with ELA channel.
Fig. 4.6 Qualitative on-state band diagram for n-channel operation.
Fig. 4.7 Effects of main-channel length on p-channel operation of FID SBTFT with ELA channel.
Fig. 4.8 Effects of main-channel length on n-channel operation of FID SBTFT with ELA channel.
Fig. 4.9 Effects of offset-channel length on p-channel operation of FID SBTFT with ELA channel.
Fig. 4.10 Effects of offset-channel length on n-channel operation of FID SBTFT with
xiv
ELA channel.
Fig. 4.11 Off-state characteristics of FID SBTFT with ELA channel at different temperatures under n-channel operation (a) VD = 1 V and (b) VD = 3 V.
Fig. 4.12 Off-state characteristics of FID SBTFT with ELA channel at different temperatures under p-channel operation (a) VD = -1 V and (b) VD = -3 V.
Fig. 4.13 Arrhenius plots of FID SBTFT with ELA channel under (a) n- and (b) p-channel operations.
Fig. 4.14 Activation energies extracted at different main-gate voltages of FID SBTFT with ELA channel.
Fig. 4.15 Qualitative off-state band diagrams for (a) n-channel operation and (b) p-channel operation.
Fig. 4.16 Off-state characteristics of FID SBTFT with SPC channel at different temperatures under n-channel operation (a) VD = 1 V and (b) VD = 3 V.
Fig. 4.17 Off-state characteristics of FID SBTFT with SPC channel at different temperatures under p-channel operation (a) VD = -1 V and (b) VD = -3 V.
Fig. 4.18 Arrhenius plots of FID SBTFT with SPC channel under (a) n- and (b) p-channel operations.
Fig. 4.19 Activation energies extracted at different main-gate voltages of FID SBTFT with SPC channel.
Fig.4-20 Energy band diagrams depicting lower EA for SPC samples due to barrier pinning by defects in SPC channel.
Chapter 5
Fig. 5.1 (a) Top view of the SB poly-Si TFT, (b) Cross-sectional view of the SB poly-Si TFT along A - A’ direction in (a), and (c) Cross-sectional view of the SB poly-Si TFT along B - B’ direction in (a). Note that the sub-gate is not
xv
shown in (c).
Fig. 5.2 Key device fabrication flow.
Fig. 5.3 Typical ambipolar ID-VG characteristics for (a) fin Structure with fin width=50nm, and (b) planar structure.Vsub = 3 Volt. VD= 0.1 and 1 Volt.
Fig. 5.4 The effect of sub-gate bias. VD= 1 Volt.
Fig. 5.5 The effect of FID length.
Fig. 5.6 Suthreshold swing degradation for both structures.
Fig.5.7 The effect of fin width on suthreshold swing. Channel length = 158 nm.
Fig. 5.8 Illustration of channel depletion layer in devices with (a) wide, and (b) narrow channels.
Fig. 5.9 The effect of fin width on threshold voltage. Channel length = 158 nm.
Fig. 5.10 The effect of sub-gate bias on threshold voltage roll-off. Fin width = 50 nm.
Fig. 5.11 Threshold voltage of FinFET device as a function of channel length for (a) with 0.1um offset length, and (b) with self-aligned spacer. Fin width is 50nm, and fin number=1.｜VG,sub｜=5V.
Fig. 5.12 Subthreshold slope as a function of fin width for FinFET device (a) with 0.1um offset length, and (b) with self-aligned spacer ｜VG,sub｜=5V.
Chapter 6
Fig. 6.1 1-D Band diagram of a gate-oxide-poly-Si channel structure. x is 0 at the oxide/poly-Si interface.
Fig. 6.2 Flow chart for determination of DOS using conventional approach.
Fig. 6.3 Flat-band voltage determination of FID SB-TFT using Tx(dlogG/dVG) vs. 1/T plots: (a) n-channel operation; (b) p-channel operation.
xvi
Fig. 6.4 Full-band DOS distribution extracted using FID SB-TFT.
Fig. 6.5 Drain current versus gate voltage characteristics.
Fig. 6.6 Arrhenius plots of Ln (dG/dVG) extracted from Fig. 6.5.
Fig. 6.7 Activation energy versus gate voltage characteristics.
Fig. 6.8 Full-band Gap state density distribution deduced by the incremental method and the temperature method.
Fig. 6.9 Ambipolar transfer characteristics under both low and high drain bias.
Fig. 6.10 Full-band gap DOS extracted at |VDS| of 0.1 and 5 V.
Fig. 6.11 (a) Ambipolar transfer characteristics, and (b) the extracted DOS results in a device with channel length of 0.8um.
Fig. 6.12 (a) Ambipolar transfer characteristics, and (b) the extracted DOS results in a device with channel length of 1um.
Fig. 6.13 (a) Ambipolar transfer characteristics, and (b) the extracted DOS results in a device with channel length of 2um.
Fig. 6.14 (a) Ambipolar transfer characteristics, and (b) the extracted DOS results in a device with channel length of 5um.
Fig. 6.15 On-current vs. channel length.
Fig. 6.16 (a), (b) Comparison of DOS extracted in devices with various channel lengths.reasonable agreement is achieved among these devices, indicating that |VDS| of 5 V is sufficient large so the effects of parasitic resistance is insignificant.
Fig. 6.17 (a) Ambipolar transfer characteristics, and (b) extracted full-band gap DOS of devices with various drain-side offset lengths at |VDS| of 0.1 V.
Fig. 6.18 (a) Ambipolar transfer characteristics, and (b) extracted full-band gap DOS of devices with various drain-side offset lengths at |VDS| of 5 V.
Fig. 6.19 Ambipolar transfer characteristics measured at 25 and 55 oC
xvii
Fig. 6.20 DOS extracted at 25 and 55 oC.
Fig. 6.21 Comparisons of DOS extracted from FID SB-TFT and Conventional TFTs.
Fig. 6.22 Full-band gap DOS of devices with SPC and as-deposited poly-Si channels.
Fig. 6.23 TEM micrographs of devices with (a) as-deposited poly-Si, and (b) SPC channel films.
Fig. 6.24 Full-band gap DOS of devices with SPC and ELA poly-Si channels.
Fig. 6.25 (a) TEM micrograph of SPC channel film.
Fig. 6.25 (b) TEM micrographs of ELA channel film.
Fig. 6.26 Ambipolar transfer characteristics of devices with and without plasma treatment.
Fig. 6.27 Full-band gap DOS before and after hydrogenation in devices with SPC channel.
Fig. 6.28 Full-band DOS before and after hydrogenation in devices with as-deposited poly-Si channel.
Fig. 6.29 Ambipolar transfer characteristics of a device with PtSi S/D.
Fig. 6.30 Full band-gap DOS of devices with CoSi2 and PtSi S/D.
Fig. 6.31 (a) Top view of poly-Si SB FinFET with self-aligned spacer; (b) Top view of poly-Si SB FinFET with offset region XD and XS. (c) Cross-sectional view along A-A+ direction in (b); (d) Cross-sectional view along B-B+ direction in (b).
Fig. 6.32 Ambipolar transfer characteristics of SB poly-Si FinFET.
Fig. 6.33 Schematic showing that higher sub-gate bias enhances source-side field emission.
Fig. 6.34 Ambipolar transfer characteristics of SB poly-Si TFT with planar structure.
Fig. 6.35 Ambipolar transfer characteristics of SB poly-Si FinFET.
Fig. 6.36 (a) Ambipolar transfer characteristics of a SB poly-Si FinFET measured at
xviii
varying temperature, (b) Flat band voltage determination.
Fig. 6.37 Full-band gap DOS of planar SB -TFT and SB FinFET.
Fig. 6.38 Comparison of VFB values determined using conventional temperature method and the new methodology performed on two groups of devices with various parameters.
Fig. 6.39 Modified Flow chart for determination of DOS density distribution
xix
Table Captions
Table 4.1 The extracted characteristic parameters of Fig. 4.2 and Fig. 4.3
Table 6.1 Gap state density of different channel films.
xx
List of Symbols
E Energy
d Polysilicon thickness EF Fermi energy
k Boltzmann constant n Electron concentration
n0 Equilibrium electron concentration Ng(E) Density of gap states (DOS) q Electronic charge
tox Gate dielectric thickness
Xo Unmodulated bulk length (or depletion width in the channel) k Boltzmann constant
T Temperature (K) VFB Flat band voltage VG Gate voltage Vth Threshold voltage εox Gate dielectric constant εsi Silicon dielectric constant μ Electron mobility
ψ band bending
ψs surface band bending of the channel ρ charge density
G conductance
G0 conductance at flat band condition
xxi
