楊伏夷

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數位系統 Digital Systems

Department of Computer Science and Information Engineering, Chaoyang University of Technology

朝陽科技大學資工系

Speaker: Fuw-Yi Yang

楊伏夷

伏夷非征番,

道德經察政章(Chapter 58)

伏

者潛藏也

道紀章(Chapter 14) 道無形象, 視之不可見者曰

夷

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Text Book: Digital Design 4th Ed.

Chap 3 Gate-Level Minimization

3.1 Introduction

3.2 The Map Method 3.3 Four-Variable Map 3.4 Five-Variable Map

3.5 Production-of-Sums Simplification 3.6 Don't-Care Conditions

3.7 NAND and NOR Implementation

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Chap 3.1 Introduction

Gate-level minimization refers to the design task of finding an optimal gate-level implementation of the Boolean

functions describing a digital circuit.

It is important that a designer understand the underlying mathematical description and solution of a problem.

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Chap 3.2 The Map Method

Boolean expression may be simplified by algebraic means as discussed in Section 2.4. However, this procedure of minimization is awkward because it lacks specific rules to

predict each succeeding step

in the manipulative process.

The map method (also known as the Karnaugh map or

K-map) provides a simple, straightforward procedure for

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Chap 3.2 The Map Method—two-variable map Figure 3.1 Two-Variable map

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Chap 3.2 The Map Method—two-variable map Figure 3.2 Representation of functions in the map

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Chap 3.2 The Map Method—three-variable map Figure 3.3 Three-variable map

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Chap 3.2 The Map Method —

Example 3.1

Simplify the Boolean function F(x, y, z) = Σ(2, 3, 4, 5)

Figure 3.4

F(x, y, z)

= Σ(2, 3, 4, 5)

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Example 3.2

Simplify the Boolean function F(x, y, z) = Σ(3, 4, 6, 7)

Figure 3.5

F(x, y, z)

= Σ(3, 4, 6, 7)

= yz + xz'

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Example 3.3

Simplify the Boolean function F(x, y, z) = Σ(0, 2, 4, 5, 6)

Figure 3.6

F(x, y, z)

= Σ(0, 2, 4, 5, 6)

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Example 3.4

a. Express F as a sum of minterms.

b. Find the minimum SOP.

Figure 3.7

F = A'C + A'B + AB'C + BC

= Σ(1, 2, 3, 5, 7)

= C + A'B

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Chap 3.3 The Map Method — Four-Variable Map

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Chap 3.3 The Map Method — Four-Variable Map

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Example 3.5

Simplify F(w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) Figure 3.9

F = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

= y'+ w' z'+ x z'

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Example 3.5

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Example 3.6

Simplify F(A, B, C, D) = A'B'C' + B'CD' + A'BCD' + AB'C' Figure 3.10

F = A'B'C' + B'CD' + A'BCD' + AB'C'

= B'C' + B'D' + A'CD' see next page

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Example 3.6

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Prime implicants

In choosing adjacent squares in a map, we must ensure that (1) all the minterms of the function are covered when we

combine the squares,

(2) the number of terms in the expression is minimized, and

(3) there are no redundant terms (i.e., minterms already covered by other terms).

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Prime implicants

A prime implicant is a product term obtained combining the maximum possible number of adjacent squares in the

map.

If a minterm in a square is covered by only one prime implicant, that prime implicant is said to be essential.

Simplify F(A, B, C, D) =

Σ(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15) See next pages

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Chap 3.3 The Map Method — prime

Two

essential prime

implicants:

BD

and

B'D'

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Fuw-Yi Yang 21

Essential prime implicants: BD and B'D'

Prime

implicants: AD,

CD, B'C, and AB'

F = BD+B'D' +CD+ AD OR BD+B'D'

+CD+ AB' OR BD+B'D'

+ B'C+ AD OR BD+B'D'

+ B'C

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Chap 3.5 Product-of-Sums Simplification Example 3.8 Simplify F(A, B, C, D) = Σ(0, 1, 2, 5, 8, 9, 10) into

a. sum-of-products form, taking the procedures as

described previously, i.e., group the squares marked by 1’s and combine them.

b. product-of-sums form. Group the squares marked by

0’s and combine them, i.e., we obtain F ' in the form of sum-of-product. Because of the generalized DeMorgan’s

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F=B'C' + B'D' + A'C'D'

F' = AB + CD + BD'

Applying

DeMorgan’s theorem to F',

F = (A' + B') +

(C' + D') +

(B' + D)

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F=B'C' + B'D' + A'C'D'

F' = AB + CD + BD'

Applying

DeMorgan’s theorem to F',

F = (A' + B') +

(C' + D') +

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Chap 3.5 Product-of-Sums Simplification

a. sum-of-products form b. product-of-sums form

These two forms can also obtain from truth table, see next page.

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Fuw-Yi Yang 27

Chap 3.5 Product-of-Sums Simplification

F(x, y, z)

= Σ(1, 3, 4, 6)

F(x, y, z)

= Π(0, 2, 5, 7)

= (x' + z')

(x + z)

See next page, note that we express F

directly in the

POS

form.

Table 3.2

x y z F

0 0 0 0 m

₀

, M

₀

0 0 1 1 m

₁

, M

₁

0 1 0 0 m

₂

, M

₂

0 1 1 1 m

₃

, M

₃

1 0 0 1 m

₄

, M

₄

1 0 1 0 m

₅

, M

₅

1 1 0 1 m

₆

, M

₆

1 1 1 0 m

₇

, M

₇

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F(x, y, z)

= Σ(1, 3, 4, 6)

F'(x, y, z)

= Σ(0, 2, 5, 7) By DeMorgan’s Theorem

F(x, y, z)

= Π(0, 2, 5, 7)

= (x' + z')

(x + z)

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Chap 3.6 Don’t Care Conditions

Functions that have unspecified outputs for some input combinations are called incompletely specified functions.

In most applications, we simply don’t care what value is assumed by the function for the unspecified minterms.

For this reason, it is customary to call the unspecified minterms of a function don’t care conditions.

These don’t care conditions can be used on a map to provide further simplification of a Boolean expression.

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Chap 3.6 Don’t Care Conditions

Example 3.9 Simplify the Boolean function F(w, x, y, z) = Σ(1, 3, 7, 11, 15)

which has the don’t care conditions

d(w, x, y, z) = Σ(0, 2, 5).

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Chap 3.7 NAND and NOR Implementation

Digital circuits are frequently constructed with NAND or

NOR

gates rather than with AND and OR gates.

NAND and NOR gates are easier to fabricate with

electronic components and are the basic gates used in all IC digital logic families.

Because of the prominence of NAND and NOR gates in the design of digital circuits, rules and procedures have

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Chap 3.7 NAND and NOR Implementation -- NAND Circuits

The NAND gate is said to be a universal gate because any digital system can be implemented with it.

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A convenient way to implement a Boolean function with NAND gates is to obtain the simplified Boolean function in terms of Boolean operators and then convert the function to NAND logic.

The conversion of an algebraic expression from AND, OR, and complement to NAND can be done by simple circuit manipulation technique that change AND-OR

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Two equivalent graphic symbols for the NAND gate are shown below. It is convenient to use them in converting AND, OR, and NOT expressions into NAND expressions.

See next page.

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Chap 3.7 NAND and NOR Implementation

-- Three ways to implement F = AB + CD (two-level)

(x')' = x

AND-OR

Equivalent

symbols of

NAND

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Chap 3.7 NAND and NOR Implementation -- Example 3.10 Two-level

Implement F(x, y, z) = Σ(1, 2, 3, 4, 5, 7) with NAND gates.

After simplification, F(x, y, z) = xy' + x'y + z

AND-OR (x')' = x

Implemented with NAND gates

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Chap 3.7 NAND and NOR Implementation -- NAND Circuits--Multilevel

There are occasions, however, when the design of digital systems results in gating structures with three or more

levels.

The most common procedure in the design of multilevel circuits is to express the Boolean function in terms of AND, OR, and complement operations. The function can then be implemented with AND and OR gares. After that, if

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Chap 3.7 NAND and NOR Implementation -- NAND Circuits--Multilevel

AND-OR

(x')' = x

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NAND Circuits--Multilevel

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Chap 3.7 NAND and NOR Implementation -- NOR Circuits

The NOR gate is said to be a universal gate because any digital system can be implemented with it.

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A convenient way to implement a Boolean function with NOR gates is to obtain the simplified Boolean function in terms of Boolean operators and then convert the function to NOR logic.

The conversion of an algebraic expression from AND, OR, and complement to NOR can be done by simple circuit manipulation technique that change OR-AND

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Two equivalent graphic symbols for the NOR gate are shown below. It is convenient to use them in converting AND, OR, and NOT expressions into NOR expressions.

See next page.

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Implementing F = (A + B) (C + D) E with NOR gates Note that OR-AND

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Implementing F = (AB' + A'B) (C + D') with NOR gates Note that OR-AND

Equivalent

symbols of

NOR

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Chap 3.8 Other Two-Level Implementations

The types of gates most often found in integrated circuits are NAND and NOR gates.

For this reason, NAND and NOR logic implementations are the most important from a practical point of view.

Some NAND and NOR gates allow the possibility of a wire connection between the outputs of two gates to

provide a specific logic function. This type of logic is

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Chap 3.8 Other Two-Level Implementations Wired logic

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Chap 3.8 Other Two-Level Implementations AND-OR-INVERT

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Chap 3.8 Other Two-Level Implementations OR-AND-INVERT

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Chap 3.8 Other Two-Level Implementations

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Chap 3.8 Other Two-Level Implementations Example 3.11

Implement the function of the following map with the four 2-level forms listed in Table 3.3.

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AND-NORÆ AND-OR-NOT F' = x'y + xy' + z combined squares of the 0’s.

Thus F = (F')' output gate NOR = OR+NOT

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NAND-ANDÆ AND-OR-NOT F' = x'y + xy' + z combined squares of the 0’s.

Thus F = (F')' = (x'y + xy' + z)' = (x'y)' (xy')' z'

output gate AND

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OR-NANDÆ OR-AND-NOT F = x'y'z' + xyz' combined squares of the 1’s.

Thus F = (F')' = ((x + y + z) (x' + y' + z))' , or-and-not.

output gate NAND = AND + NOT

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NOR-ORÆ OR-AND-NOT F = x'y'z' + xyz' combined squares of the 1’s.

Thus F = (F')' = ((x + y + z) (x' + y' + z))'

= (x + y + z)' + (x' + y' + z)', output gate OR.

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Chap 3.9 Exclusive-OR Function

The exclusive-OR (XOR), denoted by the symbol ⊕, is a logical operation that performs the following Boolean operation: x ⊕ y = x'y + xy'.

It can be shown that the exclusive-OR operation is both commutative and associative; that is,

x ⊕ y = y ⊕ x and

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Chap 3.9 Exclusive-OR Function —

AND-OR-NOT implementation

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Chap 3.9 Exclusive-OR Function -- NAND implementation

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Chap 3.9 Exclusive-OR Function --

ODD Function

x ⊕ y = x'y + xy'

x ⊕ y ⊕ z = xy'z' + x'yz' + x'y'z + xyz

The Boolean expression clearly indicates that the XOR functions are equal to 1 if and only if an odd number of variables equal to 1.

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--Parity Generation and Checking

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x Æ

Y Æ z Æ P Æ

Four bits are transmitted

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x Æ

y Æ z Æ P Æ

Four bits are transmitted

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Chap 3.10 Hardware Description Language HDL Example 3.1

module Simple_Circuit(A, B, C, D, E);

output D, E;

input A, B, C;

wire w1;

and G1(w1, A, B);

not G2(E, C);