A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique
Chun-Yu Lin, Tun-Ju Wang, Yu-Ting Hung, and Tsung-Hsien Lin
Graduate Institute of Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan thlin@ntu.edu.tw
Abstract – An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digital- to-time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz.
At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is - 135.8 dBc/Hz and it achieves 1.19 psrms integrated jitter (10 kHz to 30 MHz).
Keywords: fractional output divider, phase rotating technique
I. I
NTRODUCTIONThere are multiple sub-systems in a system-on-chips (SoC), and each sub-system or circuit requires an independent clock source for operation. To realize multiple clock sources in an SoC, implementing multiple phase- locked loops (PLLs) seems a natural method. However, multiple PLLs consumes large chip area and high power, with higher circuit complexity. Furthermore, the PLL-based clock generation has longer locking time, which is not favored in a system that require fast frequency switching. IN this regard, fractional output divider (FOD) circuit offers an alternative solution.
A conventional FOD is composed of multi-modulus divider (MMD), digital-to-time converter (DTC), and digital controller. In a FOD system, the DTC must cover one input period for phase compensation. However, the range of a DTC and the noise presents a trade-off [2]. In this work, we propose the phase-rotator-based FOD, which can reduce the range of the DTC, to realize a low-noise output clock.
II. A
RCHITECTUREFig. 1(a) depicts the block diagram of a conventional FOD.
The division ratio of a conventional FOD is determined by (N+f), where N and f is the integer and fractional frequency control words, respectively. For example, a timing operation with division ratio of 3.25 (N = 3 and f = 0.25) is shown in Fig. 1(b). The input clock is divided by 3 for three cycles and by 4 for one cycle in a repetitive method. Comparing the output clock of an MMD (MMDOUT) with ideal output clock (FOUT), we can observe the deterministic jitter, which is the blue shaded area in Fig. 1(b). It occurs repeatedly in four cycles. A DTC compensation technique is applied to cancel the deterministic jitter. In each cycle, the DTC delays the edge of MMDOUT to desired location as that of an ideal clock.
Therefore, the output jitter is eliminated by the DTC. As this diagram shown, the DTC needs to cover 1 clock period to operate properly.
Fig. 1. (a) Block diagram and (b) timing diagram of a conventional FOD.
Fig. 2 shows the block diagram of the proposed DTC- based FOD. In order to reduce the dynamic range of the DTC for improving output jitter [2], the phase rotating technique is applied. When the accumulator overflows, the phase rotator switches its output from the present phase signal to the next one which is 90o phase shifted of FIN. Since the pre- divider generates 4 quadrature signals with a division of 2, the delay range of DTC is reduced to 0.5TIN with the phase rotator.
Fig. 2 Block diagram of the proposed fractional output divider.
Fig. 3 shows the timing diagram of the proposed phase rotating technique when division ratio is set to 2.25. The fractional delay ∆T needs to be accumulated is 0.25TIN in this example. Let’s assume the delay provided by DTC, Td[0], at the first edge of FOUT is zero. After accumulating the fractional delay, Td[1] can be calculated to be 0.25TIN. The next delay, Td[2], should be 0.5TIN. However, since phase rotating technique is employed, the dynamic range of DTC is reduced to 0.5TIN. This indicates that the current signal should be rotated to next signal which is 90ˤphase shift of FIN. The overflow signal in Fig. 3 is the control signal for phase rotating. The amount of delay Td[2] after phase rotating is now reduced to 0 since the delay of 0.5TIN is transferred from DTC to the phase rotator. Besides, the phase rotating should happen inside the allowed window (blue shaded area in Fig. 3). If it occurs outside the allowed window, glitch occurs. This will cause the MMD to miscount the correct input cycles and thus result in wrong output period.
MMD DTC
FIN
Digital Control N+f
FOUT
MMDOUT
MMDOUT
FIN
FOUT TIN
(a) (b)
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Fig. 3 Timing diagram of the proposed phase rotating technique.
III. C
IRCUITI
MPLEMENTATIONFig. 4 shows the realized DTC in this work. The capacitor bank is designed to be 8 bits to achieve 1 LSB of about 1.5 ps.
Fig. 4. Architecture of the proposed DTC.
IV. M
EASUREMENTR
ESULTSThe proposed chip is fabricated in a TSMC 90-nm CMOS technology. Fig. 5 shows the chip micrograph, including two FODs. The total chip area is 1.6 mm ǘ 1.6 mm, and each FOD occupies a core area of only 0.087 mm2. Fig. 6 shows the measured transient waveforms of dual outputs. It demonstrates that dual outputs with different division ratios can be provided by the proposed FODs simultaneously.
Fig. 7 shows the phase noise measurement result when division ratio is set to 8.1289 and the output frequency is 159.923 MHz. The phase noise at 1-MHz offset is -135.8 dBc/Hz. Fig. 8 shows the measurement of frequency switching between 162.5 MHz and 159.2 MHz. The switching occurs almost immediately. Table I summarizes the chip performance and also comares with other works.
Fig. 5 Chip micrograph.
Fig. 6 Transient waveforms with dual outputs.
Fig. 7 Phase noise measurement with division ratio of 8.1289.
Fig. 8 Transient response of frequency switching.
Table I. Performance Summary and Comparison
This Work ISSCC’14 [1]
ISSCC’12 [3]
ISSCC’10 [4]
ISSCC’19 [5]
Process 90nm 65nm 180nm 180nm 28nm
Supply 1 0.9 1 1.1 0.9
Topology Frac-N Divider
Frac-N Divider
Frac-N PLL
Frac-N PLL
Frac-N Divider Frequency
Range (MHz) 0.635-162.5 20-1000 600-3600 375-3025 500-2500
Jitter (ps) 1.19* 3 10 5.51 0.09
Instantaneous
Switching Yes Yes No No Yes
Power (mW) 6.29@
160MHz
3.2@
1GHz
18.4@
3.6GHz 3.4@
75MHz 2.6 Area (mm2) 0.09 0.017 0.03 0.038 0.15
*integrated from 10k-30MHz
V. C
ONCLUSIONSA phase-rotator-based FOD is proposed in this paper. The phase rotating technique is adopted to reduce the dynamic range of DTC for output jitter improvement. Moreover, the experiments demonstrate dual outputs with different division ratios and instantaneous frequency switching. The proposed design can be applied to applications where multiple clock signals are required simultaneously.
VI. A
CKNOWLEDGEMENTThe authors thank TSRI, Taiwan, for chip fabrication.
This work is supported by MOST, Taiwan and Donation Grant FD105012.
VII. R
EFERENCES[1] A. Elkholy, et al., IEEE ISSCC, pp. 272-273, Feb. 2014.
[2] A. A. Abidi, et al., IEEE JSSC, pp. 1803-1816 Aug. 2006.
[3] W. Li, et al., IEEE ISSCC, pp. 70-72, Feb. 2012.
[4] W. Grollitsch, et al., IEEE ISSCC, pp. 478-479, Feb. 2010.
[5] S. Hung, et al., IEEE ISSCC, pp. 262-264, Feb. 2019.
MMDOUT
0°
90°
FOUT
Overflow
Td[0]=0 Td[1]=0.25TIN Td[2]=0 Phase rotate
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