High-Speed Parallel Cyclic Redundancy Check Circuit 張力元、胡大湘 ; 洪進華
E-mail: 9501987@mail.dyu.edu.tw
ABSTRACT
Error Control Coding is widely used in data communications and storage devices as a powerful method for dealing with data errors.
It also applide to many other fields such as the testing of integrated circuits and the detection of lofical faults. In this thesis, we develop the advance parallel Burst Error Correcting Code circuits. We use combinational circuit to compute syndrome and error patterns, and using FPGA board to implement our Fire Code Decoder.
Keywords : Error Control Coding, CRC, Burst Error, LFSR, FPGA Table of Contents
目錄 封面內頁 簽名頁 授權書．．．．．．．．．．．．．．．．．．．．．．．．．iii 中文摘要．．．．．．．．．．
．．．．．．．．．．．．．．iv 英文摘要．．．．．．．．．．．．．．．．．．．．．．．．v 誌謝．．．．．．．
．．．．．．．．．．．．．．．．．．．vi 目錄．．．．．．．．．．．．．．．．．．．．．．．．．．vii 圖目錄．
．．．．．．．．．．．．．．．．．．．．．．．．x 表目錄．．．．．．．．．．．．．．．．．．．．．．．．
．xii 第一章 緒論 ．．．．．．．．．．．．．．．．．．1 1.1 資料的傳輸與儲存系統 ．．．．．．．．．．．．2 1.2 歷史背景 ．．．．．．．．．．．．．．．．．．3 1.3 研究動機 ．．．．．．．．．．．．．．．．．．4 1.4 論文組織
．．．．．．．．．．．．．．．．．． 5 第二章 數學背景 ．．．．．．．．．．．．．．．．6 2.1代數介紹．．．．
．．．．． ．．．．．．．．． 6 2.1.1 Group(群組) ．．．．．．．．．．．．．．． 6 2.1.2 Field(場) ．．．．．．．．
．．．．．．．． 7 2.1.3 二進位運算．．．．．．．．．．．．．．．． 8 2.2線性區塊碼(Linear Block Codes) ．．．．．
．． 10 2.2.1 Linear Systematic Block．．．．．．．．．．11 2.2.2 Syndrome and Error Detection ．．．．．．．13 2.3 循 環碼(Cyclic Codes) ．．．．．．．．．．．．18 2.3.1 循環碼之編碼 ．．．．．．．．．．．．．．．22 2.3.2 Syndrome Computation．．．．．．．．．．． 23 2.3.3 錯誤偵測能力 ．．．．．．．．．．．．．．．23 2.4 循環冗於檢查碼計算
．．．．．．．．．．．．． 26 2.4.1 用硬體實現CRC演算法電路．．．．．．．．．．29 2.4.2 常用的CRC Polynomial
．．．．．．．．．．．29 2.5 Burst Error Correction Codes．．．．．．．． 30 2.5.1 Single-Burst-Error Correcting Codes
．．．．31 2.5.2 Fire Code．．．．．．．．．．．．．．．．．33 第三章 平行處理架構Fire Code解碼器 ．．．．．．
36 3.1 平行架構 ．．．．．．．．．．．．．．．．．．36 3.2 Syndrome Computation ．．．．．．．．．．．．37 3.3 Parallel Syndrome Computation ．．．．．．． 40 3.4 Parallel Error Pattern Computation ．．．．．46 第四章 FPGA硬體電 路實現．．．．．．．．．．．． 50 4.1 Syndrome Generator電路．．．．．．．．．．． 50 4.2 Parallel Syndrome Decoder電路．．．．．．．．51 4.2.1 Error Pattern Generator ．．．．．．．．． 52 4.3 FPGA電路架構 ．．．．．．．
．．．．．．．．．55 4.3.1電腦端傳送介面．．．．．．．．．．．．．．．59 4.3.2邏輯分析儀量測．．．．．．．．
．．．．．．．64 第五章 結論與討論 ．．．．．．．．．．．．．．．67 參考文獻．．．．．．．．．．．．．．．．
．．．． 68 圖目錄 圖1-1典型資料傳輸與儲存系統方塊圖 ．．．．．．．．．．．1 圖1-2 CRC的產生及檢查．．．．．
．．．．．．．．．．．．4 圖2-1 Systematic format of a code word ．．．．．．．．．．．11 圖2-2 Encoding circuit for a linear systematic code．．．．13 圖2-3 Syndrome circuit for a linear systematic code．．．．17 圖2-4 Encoding circuit for an cyclic code with the generator．22 圖2-5 An stage syndrome circuit ．．．．．．．．．．．23 圖2-6 LFSR CRC Circuit ．．
．．．．．．．．．．．．．．．29 圖2-7 An error-trapping decoder for burst error correcting codes．．33 圖2-8
Error-trapping decoder for the (279,265) Fire Code. ．．．．35 圖3-1 General parallel decoder for a linear block．．．．．．．
．36 圖3-2 Parallel Fire Code decoder電路架構．．．．．．．．．．37 圖3-3 Structure of Parallel CRC．．．．．．．．．
．．．．．．38 圖3-4 CRC Description．．．．．．．．．．．．．．．．．．38 圖3-5 Structure of LFSR ．．．．．．
．．．．．．．．．．．39 圖3-6 An Example of LFSR ．．．．．．．．．．．．．．．．40 圖3-7 Received Word divided into M frames．．．．．．．．．．47 圖4-1 Parallel CRC 4 Circuit．．．．．．．．．．．．．．．．50 圖4-2 Parallel CRC architecture．．．．．．．．．．．．．．．51 圖4-3 Syndrome Decoder電路．．．．．．．．．．．．．．．52 圖4-4 Syndrome Decoder ．．．．．．．．．．．．．．．．．53 圖4-5 Frame3 Burst Error Generator．．．．．．．．．
．．．．53 圖4-6 Burst Error Detector．．．．．．．．．．．．．．．．．54 圖4-7 Burst Error Corrector ．．．．．．．
．．．．．．．．54 圖4-8 FPGA Prototyping ．．．．．．．．．．．．．．．．．55 圖4-9 FPGA 內部電路架構．．．．
．．．．．．．．．．．．55 圖4-10 FPGA 詳細內部電路架構 ．．．．．．．．．．．．．56 圖4-11 RS232 腳位圖 ．．
．．．．．．．．．．．．．．．．56 圖4-12 UART串列傳輸．．．．．．．．．．．．．．．．．57 圖4-13 取樣訊號 圖．．．．．．．．．．．．．．．．．．．58 圖4-14 電腦傳送端介面程式．．．．．．．．．．．．．．．59 圖4-15 Fire code Encoder介面程式．．．．．．．．．．．．．60 圖4-16 Fire code Decoder介面程式．．．．．．．．．．．．
．60 圖4-17 Fire code Corrected介面程式．．．．．．．．．．．．61 圖4-18 模擬波形．．．．．．．．．．．．．．．
．．．．．62 圖4-19 QUARTUS II Compilation Report ．．．．．．．．．．62 圖4-20 Altera FPGA 實驗板．．．．．．
．．．．．．．．．．63 圖4-21 FPGA 量測平台 ．．．．．．．．．．．．．．．．．64 圖4-22 第一組Codeword 錯 誤Frame量測波形．．．．．．．65 圖4-23 第二組Codeword 錯誤Frame量測波形．．．．．．．65 圖4-24 第三
組Codeword 錯誤Frame量測波形．．．．．．．66 表目錄 表1-1 Type of Error Correcting Codes．．．．．．．．．．．．
．5 表2-1 Modulo-2 addition．．．．．．．．．．．．．．．．．．9 表2-2 Modulo-2 multiplication．．．．．．．．．．
．．．．．．9 表3-1 Syndrome Error Correction or Detection．．．．．．．．．50 表4-1 UART 腳位說明．．．．．．．
．．．．．．．．．．．57 表4-2 Fire Code Decoder 串並列傳輸速度面積比較．．．．．．63 REFERENCES
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