Semi-Algorithmic Test Pattern Generation
Hadi Shahriar Shahhoseini Electrical Engineering Department Iran University of Science and Technology
[email protected]
Babak Hosseini Kazerouni Electrical and Computer
Engineering Faculty Shahid Beheshti University
Abstract
Nowadays, the reliability and correctness of digital circuits has become increasingly important. In addition, digital systems design methodology has been changing to HDL-based design. Thus the test methods which are based on behavioral level design would be broadly applicable. The other factor primarily influencing the practical field of application of a specific test generation algorithm is the computational complexity of the algorithm. Random test pattern generation algorithms are much simple than the other types of algorithms.
Hence, developing such algorithms is exceedingly beneficial.
In this paper, an extension to random test pattern generation is proposed which makes it semi-algorithmic, so it is called SAT. SAT generates some parts of test vectors deterministically for the conditional nodes of the circuit’s CFG extracted from VDHL code. Simulation shows the quality of SAT generated test sets, according to path coverage, is better than ones produced by uniformly random test pattern generation.
Keywords: Design Verification, Random Test Pattern Generation, VHDL.
1. Introduction
Rapid developments in integrated circuit technology result in tremendous increase in circuit’s density.
Conversely, access to internal logic signals has become extremely limited due to use of smaller component with smaller pin spacing and less test points. The effect was a great growth in testing cost, which is a permanent part of design. The test price, and relatively the design price, can be reduced by developing more-efficient and faster test pattern generation algorithms or by the use of design techniques to enhance testability of the circuit [1]. Recent works in this area have increased emphasis on proposing test pattern generation algorithm [2], developing simulator [3], and determining the quality of generated test sequence by different coverage metrics [4-5]. Although
uniform random test pattern is the easiest, but insufficient fault coverage achieved from uniform random patterns is driving the trend of test engineers to using semi-random patterns which enhance fault coverage while maintaining the speed [6-10].
In this paper a Semi-Algorithmic Test pattern generation (called SAT) is proposed on basis of circuit’s Control Flow Graph, CFG. SAT can be applied to both logic testing and design for testability. The rest of paper is organized as follows: Section 2 describes modeling digital circuits according to CFG. Random pattern generation is reviewed in section 3 and SAT pattern generation is introduced in section 4. To evaluate SAT performance, simulation results are reported in Section 5. The paper is concluded in Section 6.
2. Control flow graph
By using a behavioral model of circuits, both the fault models and the software test generation techniques can be applied for hardware test generation. Control Flow Graph, CFG, is a modeling technique that is frequently used in software testing. In this paper CFG-based test pattern generation is studied. The CFG of a circuit is a directed graph which is noted by cfg(B), where B is the behavioral description of the circuit. This graph is illustrated by(V,E). V is the set of vertices and Eis the set of edges. Vertices represent statements of circuit's behavioral description. Edges and their directions represent the execution procedure of the VHDL description.
Here is an example from [10] that can briefly show the CFG criteria. Assume a simple VHDL code shown in Figure 1. For generating the CFG model of the VHDL code, first each line should be labeled. The corresponded CFG is shown in Figure 2. The numbers of the vertices are as same as labels for their statement in the VHDL code.
The testing process on basis of the CFG model could be stimulating the circuit by a certain input vector, a path of
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architecture Behavior of Alu is begin
alu: process begin 1: if inst =’1’ then 2: res <= A + B;
else
3: res <= A - B;
end if;
end process;
end Behavior;
Figure 1. A simple VHDL code sample
CFG is traversed which means that the VHDL statements symbolized by the graph vertices belonging to the path are executed. Design fault can be modeled as faults disturbing the CFG path traversal which means an error in execution of particular set of statements in the VHDL code. Thus a test pattern generator intends to generate a set of input vectors that would traverse higher number of paths which means improving testing quality. The set of paths for CFG of Figure 2a is shown in Figure 2b. Although CFG model can be extended to sequential circuits [10], we assume only combinational circuits in this paper. The complete explanation and the implementation of this technique can be found in [10] and [11] respectively
3. Random Test Pattern Generation
On the contrary to the deterministic approach, the random method considerably simplifies the generation of test patterns. Random process usually provides uniformly distributed random bits to the inputs; result in a simple and fast process in design verification. There are two essential phases in a random test generation algorithm [12]:
o Test pattern generation.
o Evaluation of the fault coverage
The random test generator estimates test vectors by a process generating pseudorandom input patterns. The description of a random test pattern generation algorithm mentioned in [10], summarized in Figure 3.
An example received from [10] for comprehending the random test pattern generation process. In this example we are using the behavioral description and the corresponding CFG mentioned in section 2 of this paper.
As it was stated in section 2, there are two potential paths in the CFG. It is assumed thatA, B, and inst are input ports of the circuit, A and B are four bit wide, and instis a single bit wide port. Accordingly, the input vector of the circuit is a 9-bit wide bit vector, the concatenation of the input ports. The order of the ports in the input vector is shown in the Figure 4.
(a)
Set of Paths (PΣ)
1 1 2 3
(b) Figure 2. Example of CFG and the list of paths
Figure 3. Random test pattern generation algorithm [10]
Figure 4. Example of random test pattern generation
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Three subsequent phases of the test generation process are illustrated in the figure 4. The generated input vectors, the test vector sets, and the set of covered paths are denoted by in,T and PC correspondingly. More detailed information can be found in [10].
4. SAT Pattern Generation
In this section an extension to random test pattern generation is proposed which makes it semi-algorithmic but still simple. The method, which is named SAT Pattern Generation, is constructed on basis of CFG. SAT considers conditional statements in the VHDL code.
Some examples of such statements are IF_THEN_ELSE, IF_ELSEIF_... and CASE statements which only depend on the value of one signal. We also use the fact that a vertex representing a sequential statement has only a single outgoing edge in the CFG. In contrast to this, vertices representing branch statements have multiple outgoing edges as different statements can be executed after the branch statement depending on the condition in the statement.
The pattern generation process in SAT is started with detecting vertices that have more than one outgoing edge in the CFG model of the corresponded VHDL code. Then they are sorted one after the other in the input vector (refer to Figure 4). Two attributes are assigned to each conditional statement (Ci). The first attribute, X, represents the number of signal's bit which the conditional statement depends on. The second attribute, Y, shows the number of outgoing edges in related CFG node. If Y 2 be greater than or equal to a threshold value, which X
is considered 0.5 in this paper, then in next Y times of pattern generation process, corresponding bit to C in test i vector will be selected deterministically, while the other will be random. These steps will be repeated for other conditional statements. To clarify the method, SAT is exemplified here. Assume VHDL code of Figure 5 with four signals: A, B, C and D, which are 1, 2, 3 and 3 bits signal respectively. In this VHDL code there are three conditional statements which only depend on the value of one signal, one IF statement which depends only on A, and two CASE statements which depend only on B and C.
The IF statement is shown by C and CASE statements 1 are shown by C and 2 C in Table 1. The corresponded 3 bits in the input vector and the attributes of C ,1 C , and 2
C are shown in the Table 1. For 3 C , 1 Y 2 is equal to X one which is grater than threshold value so the first couple of test vector would be:
1st A=0 GR GR GR GR GR GR GR GR 2nd A=1 GR GR GR GR GR GR GR GR
Table 1. The input vector of the VHDL code
A C1 (X=1, Y=2) B[0]
B[1] C2 (X=2, Y=3) C[0]
C[1]
C[2]
C3 (X=3, Y=3)
D[0]
D[1]
D[2]
…
if A='1' then
… else
… case B is when '00' => … when '10' => … when others => …
… case C is when '000' => … when '100' => … when others =>
…
Figure 5. A VHDL code example
where GR means Generated Randomly. By the same manner for C , the third to sixth input vector would be : 2
3rd GR B[0]=0 B[1]=0 GR GR GR GR GR GR 4th GR B[0]=0 B[1]=1 GR GR GR GR GR GR 5th GR B[0]=1 B[1]=0 GR GR GR GR GR GR 6th GR B[0]=1 B[1]=1 GR GR GR GR GR GR
Because for C the condition 3 Y 2 is not applicable, till X the end of the process input vectors will be generated randomly.
SAT can be summarized as follow:
Step1: Mark CFG nodes representing more than one edge.
Step2 :Sort them at the begin of the input vector
Step3: if Ci is not last node, assign the two variables X and Y to it, otherwise exit.
Step4 :If Y 2X is greater than or equal to a threshold value (0.5), then in next Y times of process, put the bits related toCiin test vector deterministically and assign other bits randomly. Otherwise produce all bits of the test vector randomly.
Step5: Increment i and go to step 3.
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Table 2. Percentage of covered paths in first 10 vectors
Name of the Circuit
Uniformly Random Pattern Generator Path Coverage after 10 vectors
SAT Pattern Generator Path Coverage after
10 vectors
Bit Comparator 99.5% 100%
Shift register 61.7% 62.4%
Finite State Machine 94.3% 100%
Traffic Light Controller 68.6% 68.6%
5. Simulation Results
To evaluate the SAT performance, simulation results are presented in this section. The results are compared with those of the random test generation for 4 different circuits which are studied in [10] i.e. Bit Comparator, Shift register, Finite State Machine, Traffic Light Controller. The full VHDL model of circuits can be found in [10]. One hundred test sets are generated for both SAT and uniformly random generation and each time the path converge is determined for 10 test vectors. Table 2 summarizes the results. It must be noted that for last row of table (i.e. traffic light controller) according to condition of step 4 of SAT and the CFG, the deterministic bit generation of vector is not allowed, so the path coverage are the same for both methods. Extra simulation shows if (on contrary to the mentioned condition) the deterministic bit selection was applied the path converge would be 60%.
6. Conclusion
Effective test pastern generation method improves the digital circuit testing procedure drastically. In this paper, a simple and efficient extension for random test pattern generation (called SAT) is proposed, which selects some bits of test vector deterministically, according to the attributes of branch node in the CFG. Quality of generated test sets is evaluated by simulation. According to path coverage, simulation results show that the quality of SAT generated vector is better than ones generated by a uniformly random test pattern generator.
Further research could be in the field of multi signal dependency of conditional statements. The other field for future work may be concentration on finding the best threshold value (mentioned in step 4 at SAT) by determining the number of the successor edges and nodes in the CFG, for different applications.
Acknowledgements
The authors wish to thank from Mahyar Arjomand Rad and Mild Omidi for their efforts in developing the simulation program.
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