第五章 模擬及實驗結果
5.3 實驗結果
5.3.3 三相交錯式D類放大器開迴路實驗
三相交橋式D類放大器開迴路的電感、電容以及電阻值均如前設，PWM切換頻率 為100kHz，使用三相並聯後有效切換頻率為300kHz，爲與單相的輸出波形失真比較，
仍使用200kHz取樣頻率，無效時間設定為0.5µs，因目前實驗板仍有問題未解決，未解 決的地方為取樣訊號會受到PWM切換的影響。在單相時因為使用同步取樣，故避開了 PWM切換時很大的雜訊，但在交錯式的架構中，因為每相PWM切換互差120度，故取 樣訊號很難避開PWM切換時的雜訊，造成取樣的資料錯誤，故目前尚未能完成閉迴路 實驗，這是有點美中不足之處。此開迴路實驗的輸入訊號並非使用ADC讀取，而是使 用內建的Sin Table來作輸入命令。當輸入訊號為1kHz時，其輸出電壓及輸出電流波形 如圖5.17(a)，失真約為2.15%。在同樣設定下，當輸入訊號為20kHz時，輸出電壓電流 波形如圖5.17(b)，總諧波失真為2.05%。改變輸入訊號頻率對總諧波失真之曲線如圖 5.18，因採交錯式的架構，總諧波失真如同模擬，較單相半橋式的D類放大器小很多，
雖然目前功率無法提高，可是由此波形可見得此架構的確可有效降低訊號的總諧波失 真。與圖5.11相比較，可得其結果與模擬結果近似。
圖5.17 (a)輸入1k(b)輸入20kHz弦波之交錯式D類放大器輸出電壓電流波形圖
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 104 1.8
2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Frequency(Hz)
THD(%)
Signal Frequency V.S. THD
圖5.18 交錯式D類放大器開迴路輸入訊號頻率對總諧波失真曲線圖
第 六 章
結 論
本論文研製一個以可規劃邏輯閘陣列(FPGA)為基礎全數位控制之交錯式半橋式D 類放大器，其具有低穩態輸出電壓總諧波失真、低開關切換頻率、快速動態響應的電壓 控制性能。控制器採用多迴路控制架構，包含電流內迴路與電壓外迴路，可有效降低輸 出電壓失真及諧波大小，達到輸出性能及快速響應之系統要求。在電流迴路控制器設計 中，應用電流預測型控制方法設計，具有易於實現數位控制器之優點，並且可迅速追尋 電流命令以達高頻寬之特性。在電壓外迴路控制器方面，使用比例積分(PI)控制器結合 相位領先(Phase Lead)控制器，增加電壓控制迴路頻寬。從模擬結果可知，以100kHz切 換頻率，無效時間設定為0.5µs，滿載時單相半橋式D類放大器的輸出最大總諧波失真為 12%，在相同條件下，滿載時交錯式D類放大器的輸出最大總諧波失真為1.35%，單相閉 迴路實驗最低總諧波失真為9.7%，交錯式開迴路總諧波失真均在3.8%以下，可知交錯式 的架構在不改變現有的開關切換頻率下，可有效的降低總諧波失真，確可解決在低失真 要求下，計數器式的脈寬調變產生器時脈問題。
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