文獻比較

Input Clock

Frequency 92.16MHz

31.25MHz-125MHz 833MHz 40MHz-700 MHz

DNL(LSB) -0.05~0.06

LSB N/A 4.83 LSB 0.47 LSB -1.8 LSB INL(LSB) -0.06~0.07

LSB N/A 4.47 LSB N/A -2~2 LSB Ref. Operational

Frequency

Implementation Approach

Pulse

Resolution Application

[6] 37.5 MHz DPWM

[18] 180 MHz

Triangle-wave comparison

PWM

N/A OFDM

[20] 130 MHz Analog PWM N/A WCDMA

This Work 92.16 MHz DLL-based

PWM 0.17 ns LTE

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自 傳

作者馬瑜傑，童年與青少時期在「台中」這座豐富的城市下擁抱成長，父母 從小即賦予民主、啟發的教育，讓我與哥哥從小即培養了獨立思考的能力，讓我 在高中即確立未來必定與「數理」相關科系的康莊大道努力前進。有幸自己能在

「桃園」就讀元智大學電機系，主要學習科目為電子學、電路學、電磁學，當時 選修了一些關於 IC 設計的課程，經課程修讀後，一同開啟、奠定了我對 IC 設計 的興趣。研究所即在「台北」就讀國立台灣師範大學應用電子所，也因自己擁有 喜愛獨立思考的特質，加上歷經不同城市的人文風情洗禮、刺激，更培養了自己 擁有豐富、新穎的想法，不論是身在各階段，都能運用各種方式解決種種難題。

作者在「混合信號積體電路」實驗室精進了三年半。這段期間，在郭建宏教 授麾下與臺大電子所陳怡然教授與海工所陳昭宏教授合作，共同執行國科會三年 整合型計劃。研究主題是應用在 LTE 極座標發射機之封包調變器，而這高解析高 線性調變器是由延遲鎖定迴路建構之脈波寬度調變器。作者之研究成果也投稿至 2013 年的 ASQED 會議，至馬來西亞檳城報告。此外，作者參加了教育部 100 學 年度全國大學院校積體電路(IC)設計競賽研究所/大學類比電路設計比賽得到了 設計完成獎。

學 術 成 就

[1] Chien-Hung Kuo and Yu-Chieh Ma, “A 128-phase Delay-Locked Loop with Cyclic VCDL,” 2013 5th Asia Symposium on Quality Electronic Design(ASQED), Penang, Aug. 2013, pp. 10-13.