未來展望

由於模糊雜訊分類需要進行較為複雜且瑣碎的步驟，在進行模糊推理引擎的 時候，會進行小數的計算才能得到歸屬程度，解模糊化時也需使用到除法計算，

這些要實作在硬體上都是具有挑戰及困難度的。而在演化方面，雖然已成功縮減 訓練代數，但是其訓練代數及時間還是相當可觀。因此如何將模糊雜訊分類實作 在硬體上及可考慮利用圖形處理器(Graphic Processing Unit, GPU)或是多核心程式 設計(Multi-core program)來加速訓練的演化速度是未來可以研究的方向。本研究目 前在於設計濾波器階段，濾波器設計結束之後，未來朝向硬體實作階段與濾波器 應用階段邁進。

參考文獻

[ 1 ] A. Upegui and E. Sanchez, “Evolving hardware with self-reconfigurable connectivity in xilinx fpgas,” in Proceedings of the 2006 NASA/ESA Conference on Adaptive Hardware and Systems. IEEE Computer Society, pp.

153–160, 2006.

[ 2 ] C. Lambert, T. Kalganova, and E. Stomeo, “FPGA-based systems for evolvable hardware,” in the Proceedings of the International Conference on Computer Science, ICCS-06, Mar. 2006.

[ 3 ] Ch.Ravi Kumar and S.K. Srivathsa, “EHW Architecture for Design of Adaptive Median Filter for Noise Reduction,” European Journal of Scientific Research, vol. 36, no.3, pp.473-479, 2009.

[ 4 ] D. R. K. Brownrigg, “The weighted median filter,” Communications of the ACM, vol. 27, no. 8, pp. 807–818, Aug. 1984.

[ 5 ] G. Hollingworth, S. Smith, and A. Tyrrell, “The Intrinsic Evolution of Virtex Devices Through Internet Reconfigurable Logic,” in Evolvable Systems:

From Biology to Hardware, 2000, vol. 1801. Springer Verlag, pp. 72–79.

[ 6 ] G. W. Greenwood and A. M. Tyrrell, “Introduction to Evolvable Hardware : A Practical Guide for Designing Self-adaptive Systems”, A John Wiley & Son, Inc., Publication, 2007.

[ 7 ] H. K. Kwan, “Fuzzy filters for noisy image filtering,” in Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 4, pp. 161-164, May 2003.

[ 8 ] J. F. Miller and P. Thomson, “Cartesian Genetic Programming,” in Proceedings of the 3rd European Conference on Genetic Programming

EuroGP2000, vol. 1802 of LNCS, pp 121–132, Springer Verlag, 2000.

[ 9 ] J. F. Miller and S. L. Smith, “Redundancy and Computational Efficiency in Cartesian Genetic Programming,” IEEE Transactions on Evolutionary Computation, vol. 10, no. 2, pp. 167–174, 2006.

[ 10 ] J. F. Miller, D. Job, and V. K. Vassilev, “Principles in the Evolutionary Design of Digital Circuits – Part I,” Genetic Programming and Evolvable Machines, vol. 1, no. 1, pp. 8–35, 2000.

[ 11 ] J. Hilder, J. Walker, and A. Tyrrell, “Use of a multi-objective fitness function to improve cartesian genetic programming circuits,” in Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems. IEEE Computer Society, pp. 179–185, Jun. 2010.

[ 12 ] J.R. Koza, F.H. Bennett III, D. Andre, M.A. Keane, and F. Dunlap,

“Automated synthesis of analog electrical circuits by means of genetic programming,” IEEE Transactions on Evolutionary Computation, vol. 1, no.

2, pp. 109–128, Jul. 1997.

[ 13 ] K. Arakawa, “Median filter based on fuzzy rules and its application to image restoration,” Fuzzy Sets and Systems, vol. 77, pp. 3-13, 1996

[ 14 ] L. Sekanina, “Evolutionary design of digital circuits: Where are current limits?” in Proceedings of the 2006 NASA/ESA Conference on Adaptive Hardware and Systems. IEEE Computer Society, pp. 171–178, 2006.

[ 15 ] L. Sekanina, “Evolvable components: From Theory to Hardware Implementations,” Natural Computing. Springer, 2004.

[ 16 ] L. Sekanina, “Image filter design with evolvable hardware,” in Applications of Evolutionary Computing, vol. 2002, no. 2279. Springer Verlag, pp.

255–266, 2002.

[ 17 ] L. Sekanina, “Virtual reconfigurable circuits for real-world applications of evolvable hardware,” in Proceedings of 5th International Conference on Evolvable Hardware, ICES-03, ser. LNCS, no. 2606. Springer Verlag, pp.

186–197, Mar. 2003.

[ 18 ] L.A. Zadeh, “Fuzzy sets,” Information and Control, Vol. 8, pp.338-353, 1965.

[ 19 ] M. Ahmad and D. Sundararajan, “A fast algorithm for two dimensional median filtering,” IEEE Transactions on Circuits and Systems, vol. 34, no.

11, pp. 1364 – 1374, Nov. 1987.

[ 20 ] M. Ferguson, A. Stoica, R. Zebulum, D. Keymeulen, and V. Duong, “An evolvable hardware platform based on DSP and FPTA” in Proceedings of the Genetic and Evolutionary Computing Conference, pp.145-152, Jul. 2002.

[ 21 ] M. Hubner, K. Paulsson, M. Stitz, and J. Becker, “Novel seamless design-flow for partial and dynamic reconfigurable systems with customized communication structures based on Xilinx Virtex-II FPGAs,” in Proceedings of the 18th International Conference on Architecture of Computing Systems (ARCS 2005), pp.39-44, 2005.

[ 22 ] P. Koivisto, H. Huttunen, and P. Kuosmanen, “Training-based optimization of soft morphological filters,” Journal of Electronic Imaging, vol. 5, no.3, pp.

300-322, Jul. 1996.

[ 23 ] P. Koivisto, J. Astola, V. Lukin, V. Melnik, and O. Tsymbal, “Removing Impulse Bursts from Images by Training-Based Filtering,” EURASIP Journal on Applied Signal Processing, vol. 2003, no. 3, pp. 223–237, 2003.

[ 24 ] S. J. Ko and Y. H. Lee, “Center weighted median filters and their applications to image enhancement,” IEEE Transactions on Circuits and systems, vol. 38,

pp. 984-933, Sep. 1991.

[ 25 ] S. Schulte, M. Nachtegael, V. De Witte, D. Van der Weken, and E. E. Kerre,

“A fuzzy impulse noise detection and reduction method,” IEEE Transactions on Image Processing, vol. 15, no. 5, pp. 1153-1162, 2006.

[ 26 ] S. Schulte, V.D. Witte, M. Nachtegael, D.V. der Weken, and E.E. Kerre, “A Fuzzy Two-STEP Filter for Impulse Noise Reduction From Colour Images,”

IEEE Transactions on Image Processing, vol. 15, pp. 3568-3579, 2006.

[ 27 ] T. C. Lin and P. T. Yu “Partition fuzzy median filter based on fuzzy rules for image restoration,” Fuzzy Sets and Systems, vol. 147, pp. 75-97, 2004..

[ 28 ] T. Higuchi, M. Iwata, and W. Liu, Eds., Evolvable Systems: From Biology to Hardware, in Proceedings of the First International Conference on Evolvable Systems, ICES-96, 1996.

[ 29 ] T. Martinek and L. Sekanina, “An evolvable image filter: Experimental evaluation of a complete hardware implementation in FPGA,” in Evolvable Systems: From Biology to Hardware, 2005, vol. 3637. Springer Verlag, pp.

76–85.

[ 30 ] T. Sun and Y. Neuvo, “Detail-preserving median based filters in image processing,” Pattern Recognition Letters, vol. 15, pp. 341–347, 1994.

[ 31 ] Tao Chen, Kai-Kuang Ma, Li-Hui Chen, “Tri-state median filter for image denoising,” IEEE Transactions on Image Processing, vol.8, no. 12, Dec.

1999.

[ 32 ] V. Vassilev, D. Job, and J. F. Miller, “Towards the Automatic Design of More Efficient Digital Circuits,” in Proceedings of the 2000 NASA/DoD Workshop on Evolvable Hardware. IEEE Computer Society, pp. 151–160, 2000.

[ 33 ] X. Yang and P. S. Toh, “Adaptive fuzzy multilevel median filter,” IEEE

Transactions on Image Processing, vol. 4, no. 5, pp. 680-682, May 1995.

[ 34 ] X. Yao and T. Higuchi, “Promises and Challenges of Evolvable Hardware,”

IEEE Transactions on Systems, Man, and Cybernetics – Part C, vol. 29, no.

1, pp. 87–97, 1999.

[ 35 ] Y. Zhang, S. L. Smith, and A. M. Tyrrell, “Intrinsic Evolvable Hardware in Digital Filter Design,” in Applications of Evolutionary Computing, 2004, vol.

3005, pp. 389–398.

[ 36 ] Y. Zhang, S.L. Smith, and A.M. Tyrrell, “Digital circuit design using intrinsic evolvable hardware,” in Proceedings of the 2004 NASA/DoD Conference on Evolvable Hardware, pp. 55–62, Jun. 2004.

[ 37 ] Z. Gajda and L. Sekanina, “Reducing the number of transistors in digital circuits using gate-level evolutionary design,” in Proceedings of the 9th annual conference on Genetic and evolutionary computation, pp. 245–252, 2007.

[ 38 ] Z. Vasicek and L. Sekanina, “A global postsynthesis optimization method for combinational circuits,” in Proceedings of the Design, Automation and Test in Europe, DATE. IEEE Computer Society, pp. 1–4, Mar. 2011

[ 39 ] Z. Vasicek and L. Sekanina, “An area-efficient alternative to adaptive median filtering in FPGAs,” in Proceedings of the 2007 International Conference on Field Programmable Logic and Applications. IEEE Computer Society, pp.

216–221, 2007.

[ 40 ] Z. Vasicek and L. Sekanina, “An evolvable hardware system in Xilinx Virtex II Pro FPGA,” International Journal of Innovative Computing and Applications, vol. 1, no. 1, pp. 63–73, 2007.

[ 41 ] Z. Vasicek and L. Sekanina, “Evaluation of a New Platform For Image Filter

Evolution,” in Proceedings of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems. IEEE Computer Society, pp. 577–584, 2007.

[ 42 ] Z. Vasicek and L. Sekanina, “Novel hardware implementation of adaptive median filters,” In Proceedings of the 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. IEEE Computer Society, pp.

1–6, Apr. 2008.

[ 43 ] Z. Vasicek and L. Sekanina, “Reducing the area on a chip using a bank of evolved filters,” in Evolvable Systems: From Biology to Hardware, 2007, vol.

4684. Springer Verlag, pp. 222–232.

[ 44 ] Z. Vasicek, L. Sekanina, and M. Bidlo, “A method for design of impulse bursts noise filters optimized for fpga implementations,” In Proceedings of the DATE 2010: Design, Automation and Test in Europe. European Design and Automation Association, pp. 1731–1736, 2010.

[ 45 ] Z. Vasicek, M. Bidlo, L. Sekanina, J. Torresen, K. Glette, and M.

Furuholmen, “Evolution of impulse bursts noise filters,” in Proceedings of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems. IEEE Computer Society, pp. 27–34, 2009.