第四章 氨電漿處理對元件的影響
4.5 糾結效應
糾結效 應[39, 40]也是部分空 乏(Partially-depleted)多 晶矽 薄膜 電晶體 (Polysilicon TFTs)所出現的一個非理想現象，由於懸浮的通道結構(Floating body structure)，源極到 通道的位能障很高，造成來自汲極的高電場撞擊解離(Impact ionization)的電洞(Holes)容 易被通道(Body)的缺陷捕捉(Trap)，當電洞累積越多，源極到通道的位能障降低，撞擊 解離的電洞流會由通道流入源極，形成迴路使量到的電流上升，因此需偏壓在較大的汲 極電壓將會產生此效應。
降低糾結效應最直接的方法就是限制撞擊解離的貢獻，以使汲極接面的電場降低，
包括汲極輕摻雜(LDD)、汲極補償(Drain Offset)、多重閘極(Multiple Gate)平均分攤汲極 電壓、或使用非對稱指狀結構(AF-TFTs)[41]等，都有效降低糾結效應，本實驗的元件經 過氨電漿處理一個小時後，發現可以有效的降低糾結效應，如圖4-17所示，由於通道中 的晶粒邊界缺陷數(Grain Boundary Defects)經電漿修補後能有效的降低，使能抑止糾結 效應。
Drain Current (uA)
Drain Current (uA)
Drain Voltage (V) Lg=2 um
NH3 treat 60 min Vg=6V
Vg=4.8V
Vg=3.6V 2 channel GAA TFTs
圖4-17、氨電漿處理前後Id-Vd特性。
另外實驗發現未經過電漿處理的元件，通道長度長的糾結效應較低，此說明了短通
Drain Current (uA)
Drain Voltage (V) Vg=6V
2 channel GAA TFTs
(a)
Drain Current (uA)
Drain Voltage (V) Vg=3.6V
Vg=4.8V Vg=6V 2 channel GAA TFTs
(b)
圖4-18、電漿處理前Id-Vd特性(a)Gate length 3 µm，(b) Gate length 4 µm。
4.6 背閘極 背閘極 背閘極 背閘極偏壓的影響 偏壓的影響 偏壓的影響 偏壓的影響(Back Gate Effect)
Drain Current (A)
Substrate Voltage (V)
Vb increase from -10 V to 10 V,
當Vb為負值的時候，通道下方受到電場作用會堆積電洞，使閘極電壓須加更大，才 能使通道反轉，則臨界電壓Vth變大，而當Vb漸漸加大到正值時，通道下方將逐漸吸引 電子堆積，只要外加較小的閘極電壓便能使元件進入反轉區，臨界電壓Vth變小，因此整 個元件的臨界電壓Vth將隨著基底背閘極(Back Gate)所外加的電壓而位移(Shift)[42]，如 圖4-20所示。另外，理論上GAA結構由於閘極包覆住通道，Vth不受背閘極電場影響[43]，
但我們的奈米線通道寬度不夠小且多晶矽閘極(Poly gate)的摻雜濃度為1019 cm-3，並非近 似導體，無法完全遮蔽電場的作用，因此會造成Vth位移。
-12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12
-3 -2 -1 0 1 2 3 4 5 6
Vth (@Id=1E-8 A)
Substrate Voltage (V) as-febricated
NH3 treatment 1 hr
圖4-20、背閘極偏壓對臨界電壓的影響。
2 Channel GAA TFTs W/L = 75 nm/2 um
4.7 低溫量測分析 低溫量測分析 低溫量測分析 低溫量測分析(Low Temperature Measurement)
Drain Current (A) Vd=0.5V
297K
3 treatment 2 Channel GAA TFT Lg =2um
Gate Voltage (V) (a)
Drain Current (A)
Vd=2V 2 Channel GAA TFT Lg =2um
Gate Voltage (V) (b)
-3 -2 -1 0 1 2 3 4 5 6 7 8 9 10
Drain Current (A)
Gate Voltage (V)
Vd=0.5V 2 Channel GAA TFT Lg =2um (c)
Gate Voltage (V)
Vd=2V 2 Channel GAA TFT Lg =2um
Drain Current (A)
(d)
圖4-21、不同溫度下Id-Vg轉移曲線(a)電漿處理前，Vd為0.5 V，(b)電漿處理前，Vd為2 V，
(c)電漿處理一小時，Vd為0.5 V，(d)電漿處理一小時，Vd為2 V。
首先從臨界電壓(Vth)來看，可以發現臨界電壓隨溫度減小而增加，Vth公式如下[44]，
分別為SOI與基底的摻雜濃度，Cs為SOI層的等效電容，Cbox為BOX的電容值，此觀點與 Bulk電晶體相同。
因此從公式上面可直接看出Vth位移受溫度影響，而從物理的機制上來看，直接造成 Vth位移的原因為撞擊解離所產生的電洞[45]，由於SOI層的懸浮(Floating)，使在外加汲 極偏壓下，汲極接面附近的電子受到電場加速，撞擊解離出電洞，而電洞會進入通道並
Ip0非常小(公式4-5)，為了維持I*p0小電流，V*BE不能等於零，因此會有電洞殘留，且電洞
為通道中的缺陷減少了，使次臨界斜率的擾動(Variation)減小，即元件更穩定，不受缺 陷或其它因素隨溫度擾動。Vth也是如此，經過電漿處理之後擾動減小，且幾乎不受Vd
影響，如圖4-22所示。表4-4-1與表4-4-2則為圖4-22以線性Fitting求出的斜率，即代表位 移的量大小。在漏電流方面，可看出溫度越低，漏電流越小，主要的漏電機制為熱發射 (Thermionic Emission)及Poole-Frenkel Emission，這兩個機制皆與溫度有關。熱發射機制 為在通道與汲極接面空乏區，經由晶粒邊界缺陷產生的電子電洞對，這些缺陷態(Et)能 階中被捕捉的載子獲得熱能，熱激發至導帶中，造成漏電流，為溫度強烈的函數。而
Poole-Frenkel Emission為缺陷態(Et)能階中被捕捉的載子因電場增強，使位能障夠薄或夠
低，熱激發至導帶。另外當Vg負偏壓越大，所造成的是GIDL漏電流。
50 100 150 200 250 300 -1
0 1 2 3 4 5 6 7
as-fabricated Vd 0.5V
Vd 2V Vd 0.5V Vd 2V
Vth (V)
Temperature (K) NH3 treat 1 hr
(b)
圖4-22、S.S.與Vth隨溫度變化特性(a)溫度對S.S.作圖，(b)溫度對Vth作圖。
表4-4-1、S.S.對溫度的線性擬合斜率。
S.S. NH3 1 hr No treatment Vd=0.5 V 0.249 1.152
Vd=2 V 0.252 1.170
表4-4-2、Vth對溫度的線性擬合斜率。
Vth NH3 1 hr (V/K) No treatment (V/K) Vd=0.5 V -0.0039 -0.0085
Vd=2 V -0.0038 -0.0058
第五章 第五章 第五章
第五章 結論
結論 結論
結論與 與 與未來展望 與 未來展望 未來展望 未來展望
(Summary and Future Work)
本 實 驗 利 用 側 壁Spacer及 光 微 影 製 程 技 術 ， 成 功 的 做 出 閘 極 完 全 環 繞
(Gate-All-Around)多晶矽奈米線通道的薄膜電晶體，元件經過氨電漿(NH3 Plasma)處理
後，顯示有非常優越的電性。由於閘極對通道的控制能力佳，加上電漿修補製程，有效 的減少晶粒邊界的缺陷密度(Trap Density)及降低短通道效應(Short Channel Effect)。另外 做變溫量測時，當溫度越低，可看見臨界電壓與次臨界斜率位移現象。本實驗的元件特 性與其中的兩篇參考文獻[14][26]比較，如表5-1及表5-2所示，雖然不是每項參數都是最 好，但優越的特性在於經過電漿修補後，其改善的幅度相當大，此說明當元件的製作過 程中，由於通道需經由BOX濕蝕刻製程，使通道懸空，此時通道會因應力的關係，造成
更多斷鍵(Dangling Bond)，但電漿修補後，此GAA結構的特性才會顯現出來。表5-1為
同樣是Side-Wall Spacer製程所形成的奈米線薄膜電晶體，參數萃取條件為Vd=0.5 V，而
表5-2為所有參數萃取條件在Vd=2 V，但載子遷移率(Mobility)萃取條件在Vd=0.05 V。
目前環繞式閘極結構的薄膜電晶體只做到單顆的電晶體，未來可朝記憶體ONO結構 或多位元的快閃記憶體方面進行，絕緣材料可以高介電係數(High-k)材料取代，來降低 工作電壓及功率消耗，並實現陣列式積體電路化，另一方面本實驗的元件應用到主動式 陣列平面顯示器(AMLCD)的面板驅動電路，讓面板整個亮度提高且更均勻，反應速度也 得到改善。製程方面可改為電子束微影(E-beam lithography)，可提升元件製作速度，產
量與良率(yield)皆會獲得改善，且可縮短閘極長度，達到更小的元件尺寸。
表5-1、本實驗元件和文獻參考[14]之比較。
‧
2-Channel Devices *: Average IEEE,2006Single Gate TEOS:30 nm (W/L=21 nm×2/ 2 um)
This Study Gate All Around
TEOS:27 nm (W/L=75 nm×2/ 2 um)
SPC
SPC (NH3 1hr)
SPC
SPC (NH3 1hr)
Vth (V) 7.27 2.54 4.07 4.5* -0.2 -0.17*
S.S. (mV/dec) 381 194 390 425* 116 126*
Ion/Ioff ratio (108) 0.163 0.536 0.065 0.11* 1.13 2.73*
Mobility(cm2/V·s) 55 73 26.4 26* 54.9 50.2*
表5-2、本實驗元件和文獻參考[26]之比較。
‧
Multi-Channel Devices *: Average APL, 2004Tri-gate LDD TEOS:26 nm
This Study Gate All Around
TEOS:27 nm SPC-SC
1 um/ 0.5 um (NH3 1hr)
SPC-MNC 67 nm×10/ 0.5 um
(NH3 1hr)
SPC 75 nm×8/ 2 um
(No NH3)
SPC 75 nm×8/ 2 um
(NH3 1hr)
Vth (V) -0.11 0.23 2.92 2.4* 0.6 0.16*
S.S. (mV/dec) 360 110 466 439.5* 107 131.2*
Ion/Ioff ratio (108) 0.59 4.73 0.41 0.69* 5.25 7.86*
Mobility(cm2/V·s) 34.01 32.5 17.6 18.2 * 56.3 44.1*
參考文獻
Electronics, vol. E85-C, no. 5, pp. 1073-1078, 2002.[2] J. Y. Song, W. Y. Choi, J. H. Park, J. D. Lee, and B.-G. Park, "Design Optimization of Gate-All-Around (GAA) MOSFETs," IEEE Trans. on Nanotechnology, vol. 5, no. 3, pp.
186-191, 2006.
[3] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R.
Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "High-Performance Fully Depleted Silicon Nanowire (Diameter ≤ 5 nm) Gate-All-Around CMOS Devices," IEEE Electron Device Letters, vol. 27, no. 5, pp. 383-386, 2006.
[4] H. Lee, S.-W. Ryu, J.-W. Han, L.-E. Yu, M. Im, C. Kim, S. Kim, E. Lee, K.-H. Kim, J.-H.
Kim, D.-I. Bae, S. C. Jeon, K. H. Kim, G. S. Lee, J. S. Oh, Y. C. Park, W. H. Bae, J. J.
Yoo, J. M. Yang, H. M. Lee, and Y.-K. Choi, "A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices," IEEE Symposium on VLSI Technology, pp. 144-145 , 2007.
[5] A. Burenkov, J. Lorenz, "Corner Effect in Double and Triple Gate FinFETs," European Solid-State Device Research, pp. 135-138, 2003.
[6] S. Miyamoto, S. Maegawa, S. Maeda, T. Ipposhi, H. Kuriyama, T. Nishimura, and N.
Tsubouchi, "Effect of LDD Structure and Channel Poly-Si Thinning on a Gate-All-Around TFT (GAT) for SRAM’s," IEEE Trans. on Electron Devices, vol. 46, no.
8, pp. 1693-1698, 1999.
[7] Y. Yamamoto, T. Hidaka, H. Nakamura, H. Sakuraba, and F. Masuoka, "Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and GateWork Function Engineering," IEICE Trans. on Electronics, vol. E89–C, no.4,
pp.560-567, 2006.
[8] S. Cristoloveanu, "Future Trends in SOI Technologies," Journal of the Korean Physical Society, vol. 39, pp. S52-S55, 2001.
[9] T. J. King, “Impact of low temperature polysilicon on the AMLCD market,” Solid State Tech., pp. 406-410, 2000.
[10] T. Serikawa, S. Shirai, A. Okamoto, and S. Suyama, "Low-Temperature Fabrication of High-Mobility Poly-Si TFT’s for Large-Area LCD’s," IEEE Trans. on Electron Devices, vol. 36, no. 9, pp. 1929-1933, 1989.
[11] Y. Cui, Q. Wei, H. Park, C. M. Lieber, “Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species,” Science, vol. 293, pp. 1289-1292, 2001.
[12] S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. S. Lin, B. H. Tseng, J. H. Shy, S. M.
Sze, C. Y. Chang, and C. H. Lien, "A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory," IEEE Electron Device Letters, vol. 28, no. 9, pp. 809-811, 2007.
[13] X. Duan, C. Niu, V. Sahi, J. Chen, J. W. Parce, S. Empedocles, and J. L. Goldman,
“High-performance thin-film transistors using semiconductor nanowires and nanoribbons,” Nature, vol.425, pp.274-278, 2003.
[14] Y. C. Wu, T. C. Chang, C. Y. Chang, C. S. Chen, C. H. Tu, P. T. Liu, H. W. Zan, and Y.
H. Tai, "High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure," Applied Physics Letters, vol. 84, no.
19, pp. 3822-3824, 2004.
[15] O. H. Elibol, D. Morisette, D. Akin, J. P. Denton, and R. Bashir, "Integrated nanoscale silicon sensors using top-down fabrication," Applied Physics Letters, vol. 83, no. 22, pp.
4613-4615, 2003.
[16] S. Bourland, J. Denton, A. Ikram, G. W. Neudeck, and R. Bashird, "Silicon-on-insulator
processes for the fabrication of novel nanostructures," American Vacuum Society, vol. B 19, no. 5 , pp.1995-1997, 2001.
[17] H. Cho, P. Kapur, P. Kalavade, and K. C. Saraswat, "A Novel Spacer Process for Sub-10 nm-Thick Vertical MOS and Its Integration With Planar MOS Device," IEEE Trans. on Nanotechnology, vol. 5, no. 5, pp. 554-563, 2006.
[18] H. C. Lin, M. H. Lee, C. J. Su, T. Y. Huang, C. C. Lee, and Y. S. Yang, "A Simple and Low-Cost Method to Fabricate TFTs With Poly-Si Nanowire Channel," IEEE Electron Device Letters, vol. 26, no. 9, pp. 643-645, 2005.
[19] Y. A. Tarakanov, and J. M. Kinaret, "A Carbon Nanotube Field Effect Transistor with a Suspended Nanotube Gate," Nanoletters, vol. 7, no. 8, pp. 2291-2294, 2007.
[20] C. Y. Meng, B. L. Shih, and S. C. Lee, "Silicon nanowires synthesized by vapor–liquid–solid growth on excimer laser annealed thin gold film," Journal of Nanoparticle Research, pp. 657-660, 2007.
[21] S. K. Sung, D. H. Kim, J. S. Sim, K. R. Kim, Y. K. Lee, J. D. Lee, S. D. Chae, B. M.
Kim, and B. G. Park, "Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology," Japanese Journal of Applied Physics, vol. 41, no. 4B, pp. 2606-2610, 2002.
[22] H. C. Cheng, L. J. Cheng, C. W. Lin, Y. L Lu, and C. Y. Chen, "High performance low-temperature processes polysilicon TFTs fabricated by excimer laser crystallization with recessed-channel structure," IEEE AMLCD Technical Digest, pp. 281-285, 2000.
[23] C. J. Su, H. C. Lin, and T. Y. Huang, "High-Performance TFTs With Si Nanowire Channels enhanced by Metal-Induced Lateral Crystallization," IEEE Electron Device Letters, vol. 27, no. 7, pp. 582-584, 2006.
[24] S. W. Lee, and S. K. Joo, “Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization,” IEEE Electron Device Letters, vol. 17, no. 4, pp.
160-162, 1996.
[25] T. Little, H. Koike ,and H. Koike, “Low Temperature Poly-Si TFTs Using Solid Phase Crystallization of Very Thin Films and Electron Cyclotron Resonance Chemical Vapor Deposition Gate Insulator,” Japanese Journal of Applied Physics, vol. 30, no. 30, pp.
3724-3728, 1991.
[26] H. C. Lin, M. H. Lee, C. J. Su, and S. W. Shen, "Fabrication and Characterization of Nanowire Transistors With Solid-Phase Crystallized Poly-Si Channels," IEEE Trans. on Electron Devices, vol. 53, no. 10, pp. 2471-2477, 2006.
[27] M. K. Hatalis, and D. W. Greve, “Large grain polycrystalline silicon by low-temperature annealing of low-pressure chemical vapor deposited amorphous silicon films,” Journal of Applied Physics, vol. 63, pp. 2260-2266, 1988.
[28] U. Koster, "Crystallization of amorphous silicon films," Physica Status Solidi A, vol. 48, pp. 313-321, 1978.
[29] C. K. Yang, C. L. Lee, and T. F. Lei, "Enhanced H2-Plasma Effects on Poly silicon Thin-Film Transistors with Thin ONO Gate-Dielectrics," IEEE Electron Device Letters, vol. 16, no. 6, pp. 228-229, 1995.
[30] C. K. Yang, T. F. Lei, and C. L. Lee, "Improved Electrical Characteristics of Thin-Film Transistors Fabricated on Nitrogen-Implanted Polysilicon Films," IEEE Electron Devices Meeting, pp. 505-508, 1994.
[31] T. Unagami, and T. Takesida, "High-Performance Poly-Si TFT’s with ECR-Plasma Hydrogen Passivation," IEEE Trans. on Electron Devices, vol. 36, no. 3, pp. 529-533, 1989.
[32] A. Yin, and S. J. Fonash, "High-Performance P-Channel Poly-Si TFT’s Using Electron Cyclotron Resonance Hydrogen Plasma Passivation," IEEE Electron Device Letters, vol.
15, no. 12, pp. 502-503, 1994.
[33] H. N. Chern, C. L. Lee, and T. F. Lei, "The Effects of Fluorine Passivation on Polysilicon Thin-Film Transistors," IEEE Trans. on Electron Devices, vol. 41, no. 5, pp.
698-702, 1994.
[34] H. C. Cheng, F. S. Wang, and C. Y. Huang, "Effects of NH3 Plasma Passivation on N-Channel Polycrystalline Silicon Thin-Film Transistors," IEEE Trans. on Electron Devices, vol. 44, no. 1, pp. 64-68, 1997.
[35] C. W. Lin, M. Z. Yang, C. C. Yeh, L. J. Cheng, T. Y. Huang, H. C. Cheng, H. C. Lin, T.
S. Chao, and C. Y. Chang, "Effects of Plasma Treatments, Substrate types, and Crystallization Methods on Performance and Reliability of Low Temperature Polysilicon TFTs," IEEE Electron Devices Meeting, pp. 305-308, 1999.
[36] F. S. Wang, M. J. Tsai, and H. C. Cheng, "The Effects of NH3 Plasma Passivation on Polysilicon Thin-Film Transistors," IEEE Electron Device Letters, vol. 16, no. 11, pp.
503-505, 1995.
[37] M. V. Dunga, A. Kumar, and V. R. Rao, "Analysis of Floating Body Effects in Thin Film SOI MOSFETs using the GIDL Currlent Technique," IEEE Physical and Failure Analysis of Integrated Circuits, pp. 254-257, 2001.
[38] H. S. Byun, W. S. Lee, J. W. Lee, K. H. Lee, Y. K. Park, J. T. Kong, "3-Dimensional Analysis on the GIDL Current of Body-tied Triple Gate FinFET," IEEE Simulation of Semiconductor Processes and Devices, pp. 267-270, 2006.
[39] J. P. Colinge, "Reduction of Kink Effect in Thin-Film SOI MOSFET’s," IEEE Electron Device Letters, vol. 9, no. 2, pp. 97-99, 1988.
[40] S. C. Lin, and J. B. Kuo, "Temperature-Dependent Kink Effect Model for Partially-Depleted SOI NMOS Devices," IEEE Trans. on Electron Devices, vol. 46, no. 1, pp. 254-258, 1999.
[41] L. Mariucci, G. Fortunato, A. Bonfiglietti, M. Cuscuna, A. Pecora, and A. Valletta,
"Polysilicon TFT Structures for Kink-Effect Suppression," IEEE Trans. on Electron Devices, vol. 51, no. 7, pp. 1135-1142, 2004.
[42] F. Dauge, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah, B. Y.
Nguyen, "Coupling effects and channels separation in FinFETs," Solid-State Electronics, vol. 48, pp. 535-542, 2004.
[43] N. Singh, A. Agarwal, L.K. Bera, R. Kumar, G.Q. Lo, B. Narayanan, and D.L. Kwong,
"Gate-all-around MOSFETs: lateral ultra-narrow (≤10 nm) fin as channel body,"
Electronics Letters, vol. 41, no. 24, pp. 1353-1354, 2005.
[44] Y. Omura, A. Nakakubo, H. Nakatsuji, "Quantum mechanical effect in temperature dependence of threshold voltage of extremely thin SOI MOSFETs," Solid-State Electronics, vol. 48, pp. 1661-1666, 2004.
[45] J. Wang, N. Kistler, J. Woo, and C. R. Viswanathan, "Threshold Voltage Instability at Low Temperatures in Partially Depleted Thin-Film SOI MOSFET’s," IEEE Electron Device Letters, vol. 12, no. 6, pp. 300-302, 1991.
[46] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K.
M. Hoe, S. R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices:
Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance,"
IEEE Electron Devices Meeting, pp. 1-4, 2006.