5.1 總結
在本論文中所提出的四倍取樣之三角積分調變器使用 TSMC 0.18 m 1P6M 標準 CMOS 製程來實現，在供應電壓為 1.8 V，系統頻寬為 20 kHz，等效的取樣 頻率為 10 MHz，所得到的訊號雜訊比為 71.37 dB，總消耗功率為 2.61 mW，整體 面積大小為 1.45*2.46 mm2。利用 FOM(Figure Of Merit, FOM)效能指標與歷年來 得相關文獻做比較，如(6-1)式所示，其中 Power 為總消耗功率，ENOB 為有效位 Goes[26]
2010
5.2 未來展望
本論文所體出的四倍取樣之三角積分調變器，與第四章所提出的重疊積分時 脈，利用簡易的電路架構提升整體系統的解析度，且使用創新的重疊積分時脈想 法，降低三角積分器的功率消耗。元件設計上也盡量達到最佳化的設計。
以下幾點為四倍取樣之三角積分調變是需要進一步探討的問題。
1. 設計上採用四路徑的取樣電路做為三角積分調變器的訊號取樣端，開關數目 比較起傳統三角積分調變器多出許多，若能使各開關等校電阻更為線性，相 信會對整體系統的輸出表現提升許多。另一方面，為實現四倍取樣架構採用 最簡易且易實現的分散式回授串聯積分器架構，若能嘗試使用不同的調變器 架構實現電路，降低架構對於開關與運算放大器的敏感性，進而改善整體性 統的輸出表現
2. 呈上一點，開關數目增加控制訊號的多寡必然隨之上升，離散三角積分調變 器雖對於時脈抖動效應較為不敏感，但對於時序間隔安排則極為重要。電路 佈局時應多加考慮控制訊號與回授訊號走線上的寄生電容效應，使訊號在實 際電路中能夠如模擬時的時序安排相當，進而提升實際聯測後的輸出表現。
3. 在取樣與積分時脈相位的分配上也值得進一步研究，所提出的三角積分調變 器若再搭配雙路徑取樣架構來實現，是否可進一步達到八倍取樣的操作速率 的效果。
參 考 文 獻
[1] J. M. de la Rosa, “Sigma-Delta Modulator: Tutorial overview, design guid, and state-of-the-art survey,” IEEE Trans. Circuit Syst. I, Reg. Papers, vol. 58no.1,pp. 1-21, Jan.2011.
[2] D. A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
[3] R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, Second Edition, Wiley, IEEE Press, 2008.
[4] J. Silva, U. K. Moon, J. Steensgaard, and G. C. Temes, “Wideband Low-Distortion Delta-Sigma ADC Topology,” Electron. Lett., vol. 37, pp.737-738, Jun. 2001.
[5] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters: New York:
Wiley, 2004.
[6] K. C. H. Chao, S. Nadeem, W. L. Lee,and C. G.Sodini, “A Higher-Order Topology for Interpolative Modulators for Oversampling A/D Converters,” IEEE Trans. Circuits Syst., vol. 37, no. 3, pp. 309-318, Mar. 1990.
[7] W. L. Lee and CC. G. Sodini, “A Topology for Higher-Order Interpolative Coders,” in proc. IEEE Intel. Symp. Circuits Syst., 1987, pp. 459-462
[8] B. DelSignore, D. Kerth, N. Sooch, and E. Swansoon, “A Monolithic 20-B Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, col. 25, no. 6, pp.1311-1317, Dec. 1990.
[9] T. Tille, J. Sauerbrey, and D. Schmitt-Landsiedel, “A Low-Voltage MOSFET-only Δ
Modulator for Speech Band Applications Using Depletion-Mode MOS-Capacitors in Combined Series and Parallel compensation,” in Proc. IEEE Intel. Symp. Circuits Syst., May 2001, pp. 376-379.
[10] J. Sauerbrey, T. Tille, D. S. Landsiedel, and R. Thewes, “A 0.7-V MOSFET-Only Switched-OpampΔ Modulator in Standard Digital CMOS Technology,” IEEE J. Solid-State Circuits, vol. 37, no.12, pp. 1622-1669 Dec. 2002.
[11] P. Favart, P. Deval, and M. J. Declercq, “An improved voltage doubler in a standard CMOS technology,” in Proc. IEEE Intel. Symp. Circuits Syst., Hong Kong, June 1997, pp. 249-252.
[12] P. Favart, P. Deval, and M. J. Declercq, “A high-efficiency CMOS voltage doubler,” IEEE J. solid-State Circuits, vol. 33, no. 33,pp. 410-416, Mar. 1998.
[13] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched opamp circuits,” Electron. Lett., vol. 35, no. 1, pp. 8-10, Jan.1999.
[14] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-W 88-dB audio sigma-delta modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1809-1818, Nov. 2004.
[15] J. Goes. B. Vaz, R. Monteiro, and N. Paulino, “A 0.9 V modulator with 80 dB SNDR and 83 dB DR using single-phase technique,” in Proc. IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 191-200.
[16] E. Bilhan and F. Maloberti, “A wide-band sigma-delta modulator with cross-coupled two-paths,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp. 886-893, May 2009.
[17] K.-T. Tiew and M. Je, ”A 0.06-mm2 double-sampling single-OTA 2nd-order Δ modulator in 0.18-m CMOS technology,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2011, pp.253-256.
[18] A. Nilchi and D. A. Johns, “A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator,” IEEE Trans. Circuits Syst. I, Page(s): 1310-1321, May 2013.
[19] R. Khoini-Poorfard and D. A. Johns, “Time-interleaved oversampling converters,”
Electron. Lett., vol. 29, no. 19, pp. 1673-1674, Sept. 1993.
[20] R. Khoini-Poorfard, L. B. Lim, and D. A. Johns, “Time-interleaved oversampling A/D converters: theory and practice,” IEEE Trans. Circuits Syst. II, vol. 44, pp. 634-645, Aug.
1997.
[21] H. K. Yang and E. I. EI-Masry, “Double sampling delta-sigma modulators,” IEEE Trans.
Circuits Syst. II, col. 43, pp. 524-529, July 1996.
[22] Chien-Hung Kuo, Chang-Hung Chen, Huang-Shih Lin, Shen-Iuan Liu, "A tunable bandpass Δ modulator using double sampling", Circuits and Systems 2005. ISCAS 2005.
IEEE International Symposium on, pp. 3676-3679 Vol. 4, 2005.
[23] P. Rombouts, J. Raman, L. Weyten, "An approach to tackle quantization noise folding in double-sampling Δ modulation A/D converters", Circuits and Systems II: Analog and Digital Signal Processing IEEE Transactions on, vol. 50, pp. 157-163, 2003, ISSN 1057-7130.
[24] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc. New York, NY, USA, 2011.
[25] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-uW 88dB audio sigma-delta modulator in 90-nm CMOS,” IEEE Journal Solid-State Circuits, vol. 39, no. 11, pp. 1809-1818, Nov.2004.
[26] J. Goes, B. Vaz, R. Monteiro, and N. Paulino, “A 0.9 V Δ modulator with 80 dB SNDR and 83 dB DR using a single-phase technique”, in IEEE ISSCC Dig. Tech. Papers, 2006, pp.74-75.
[27] Chien-Hung Kuo, Deng-Yao Shi and Kang-Shuo Chang, “A Low-Voltage Fourth-Order Cascade Delta–Sigma Modulator in 0.18-um CMOS”, IEEE Transactions on Circuits and Systems I,vol. 57 , no. 9 pp.2450-2461, Sep.2010.
[28] L. Liu, D Li, L. Chen, Y. Ye, and Z. Wang, “A 1-V 15Bit Audio DS –ADC in 0.18um CMOS”, IEEE Trans. on circuits and systems I. Reg. papers, vol. 59, no.5, pp. 915-925, MAY.2012.
[29] Taewook Kim, Changsok Han, and Nima Maghari, “A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator”, Symposium on VLSI Circuit, June 2015, C258-C259.
作 者 簡 歷
作者曾煒崴，民國八十一年三月出生於台中縣。於民國九十六年就讀國立大 甲高工資訊科開始接觸電子資訊領域，遂後就讀國立臺灣師範大學應用電子科技 學系，研究所直升電機工程所系所。經兩年多時間於混合信號積體電路實驗室接 受郭建宏較指導，除專研類比電路設計外，在學期間參與國際研討會，參加類比 IC 設計競賽與 CIC 開設之課程，另外也擔任實驗室負責人與管理實驗室伺服器。
至此學習許多專業項目與人際溝通，並於民國一零六年二月完成碩士學位。
學 術 成 就
[1] Chien-Hung Kuo, Wei-Wei Tseng, “A Quadruple-Sampling Second-Order Delta-Sigma Modulator ”, 2016 IEEE 5th.Global Conference on Consumer Electronics, Kyoto, Oct.
2016, pp. 1-2.