• 沒有找到結果。

τ

L

, τ

H

(S )

τ L

τ H

1.2 1.3 1.4 1.5 1.6

10

-2

10

-1

10

0

Vg (V)

strong inversion

τ

L

, τ

H

(S )

τ L

τ H

Fig. 5-15 The electron occupation factor (f

t) and normalized noise power spectral density versus gate voltage in a small area n-MOSFET (W/L=

0.16µm/0.12µm, tox=15Å). The second noise peak in strong inversion is due to valence-band electron

0.6 0.9 1.2 1.5 1.8

weak inversion strong inversion valence electron tunneling

induced noise

weak inversion strong inversion valence electron tunneling

induced noise

Fig. 5-16 Electron occupation factor (f

t) and

normalized noise power spectral density in a small

=33Å n-MOSFET (W/L= 0.24µm/0.18µm,).

0.5 1.0 1.5 2.0 2.5

small area n-MOSFET (W/L=0.24µm/0.18µm)

small area n-MOSFET (W/L=0.24µm/0.18µm)

small area n-MOSFET (W/L=0.24µm/0.18µm)

small area n-MOSFET (W/L=0.24µm/0.18µm)

Chapter 6 Conclusions

First of all, the hot carrier degradation mechanisms of drain current flicker noise in analog CMOS devices are investigated. The sources responsible for noise degradation are verified through both submicron CMOS transistors and a special ONO charge storage cell with various kinds of stresses. From our observation, the non-uniform oxide-trapped charges generated by maximum gate current stress could give rise to series flicker noise degradation as the number fluctuation mechanism dominates noise processes, which can be understood through a two-region unified flicker noise model. For n-MOSFETs, the number fluctuation mechanism dominates at low gate bias, so that the noise magnitude seriously increases after hot carrier stressing.

Next, pocket implantation effects on drain current flicker noise in 0.13µm CMOS process based high performance analog n-MOSFETs is investigated. Our results show that pocket implantation will degrade device noise characteristics primarily due to enhanced non-uniform threshold voltage distribution along the channel. Besides, the oxide quality is not affected by the pocket implantation process through the evidence of charge pumping results.

That is, the channel profile engineering would be a key factor for low noise device design instead of the improvement of oxide quality. In addition, an analytical flicker noise model to take into account a pocket doping effect is proposed and shows good agreement with the measurement results. The analytical model is easy to implement in circuit simulators, such as HSPICE, for analog circuit design. Based on this concept, the programming charge distribution in NROM cells can be extracted from noise measurement in the linear operation regime without any device simulations. In addition, the result shows good agreement with the inverse modeling method.

Then, the pocket implantation would influence the channel carrier distribution and

degrade drain current Flicker noise, which is proved by device simulation. In addition, substrate bias has large effect on low frequency noise. The noise level is increased at a reverse substrate bias. This effect is more significant in a pocket device since the reverse substrate bias will result in a more non-uniform threshold voltage distribution. In addition, the reduction of channel carrier number due to a reverse substrate bias also contributes to the increase of noise.

Finally, low frequency flicker noise in analog n-MOSFETs with 15Å gate oxide is investigated. A new noise generation mechanism resulting from valence band electron tunneling is proposed. In strong inversion condition, valence-band electron tunneling from Si substrate to poly-gate takes place and results in the splitting of electron and hole quasi Fermi-levels in the channel. The excess low frequency noise is attributed to electron and hole recombination at interface traps between the two quasi Fermi-levels. Random telegraph signal due to capture of channel electrons and holes is characterized in a small area device to support our model.

REFERENCES

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[1-20] G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectronics Reliability, vol. 42, pp. 573-582, 2002.

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Chapter 2

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[2-3] E. Simoen, P. vasnia, J. Sikula, and C. Clayes, “Empirical model for the low-frequency noise of hot-carrier degraded submicron LDD MOSFETs,”

IEEE Electron Device Lett., vol. 18, pp. 480-483, 1997.

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[2-11] R. Brederlow, W. Weber, D. S.-Landsiedel, and R. Thewes, “Hot carrier degradation of the low frequency noise of MOS transistors under analog operating conditions,” in Proc. Int. Reliab. Phys. Symp., pp. 239-242, 1999.

[2-12] E. Simoen, P. Vasina, J. Sikula, and C. Claeys, “Empirical model for the low-frequency noise of hot-carrier degraded submicron LDD MOSFET’s,”

IEEE Electron Device Lett., vol. 18, pp. 480-482, 1997.

[2-13] E. Simoen and C. Claeys, “Hot-carrier stress effects on the amplitude of random telegraph signals in small area Si P-MOSFETS,” Microelectron Reliability, vol. 37, pp. 1015-1019, 1997.

[2-14] M. H. Tsai and T. P. Ma, “1/f noise in hot-carrier damaged MOSFET’s: effects of oxide charge and interface traps,” IEEE Electron Device Lett., vol. 14, pp.

256-258, 1993.

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Chapter 3

[3-1] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A physics-based MOSFET noise model for circuit simulators,” IEEE Trans. Electron Devices, vol. 37, pp.

1323-1333, 1990.

[3-2] A. van der Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986.

[3-3] Ali Hajimiri, and Thomas H. Lee, “A general theory of phase noise in electrical oscillators” IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, 1998.

[3-4] A. Chatterjee, K. Vasanth, D. T. Crider, M. Nandakumar, G. Pollack, R.

Aggarwal, M. Rodder and H. Shichijo, “Transistor design issues in integrating analog functions with high performance digital CMOS,” in Symp. VLSI Tech.

Dig., pp. 147-148, 1999.

[3-5] Q. Li and J. S. Yuan, “Linearity analysis and design optimization for 0.18µm CMOS RF mixer,” in IEE Proceedings on Circuits, Devices and Systems, pp.

112-118, 2002.

[3-6] Hemant V. Deshpande, Baohong Cheng, and Jason C. S. Woo, “Analog device design for low power mixed mode applications in deep submicron CMOS technology,” IEEE Electron Device Lett., vol. 22, pp. 588-590, 2001.

[3-7] T. Ohguro, H. Naruse, H. Sugaya, H. Kimijima, E. Morifuji, T. Yoshitomi, T.

Morimoto, H. S. Momose, Y. Katsumata, and H. Iwai, “0.12mm raised gate/source/drain epitaxial channel NMOS technology,” in IEDM Tech. Dig., pp. 927-930, 1998.

[3-8] T. Ohguro, R. Hasumi, T. Ishikawa, M. Nishigori, H. Oyamatsu, and F.

Matsuoka, “An epitaxial channel MOSFET for improving flicker noise under low supply voltage,” in Symp. VLSI Tech. Dig., pp. 160-161, 2000.

[3-9] M. H. Tsai and T. P. Ma, “The impact of device scaling on the current fluctuations in MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, pp.

2061-2068, 1994.

[3-10] J. W. Wu, H. C. Chang, and T. Wang, “Oxide soft breakdown effects on drain current flicker noise in ultra-thin oxide CMOS devices,” in Proc. SSDM, pp.

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[3-12] R. Brederlow, W. Weber, D. S.-Landsiedel, and R. Thewes, “Fluctuations of the low frequency noise of MOS transistors and their modeling in analog and RF-circuits,” in IEDM Tech. Dig., pp. 923-926, 1999.

[3-13] R.G.-H. Lee, Jen-Shien Su and S.S. Chung, “A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFET’s,” IEEE Trans. Electron Devices, Vol. 43, pp. 81-89, 1996.

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Chapter 4

[4-1] E. Simoen, C. claeys, “Substrate bias effect on the excess noise behavior of MOS transistors,” J. Appl. Phy., Vol. 77, pp. 910-917, 1995.

[4-2] Tsun-Lai Hsu, Denny Duan-Lee Tang and Jeng Gong, “Low-frequency noise properties of dynamic-threshold (DT) MOSFET’s,” IEEE Electron Device Lett., Vol. 20, pp. 532-534, 1999.

[4-3] H. Ueno, D. Kitamaru, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H. J.

Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama,

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[4-4] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko and Chenming Hu,

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[4-5] M. J. Deen and O. Marinov, “Effect of forward and reverse substrate biasing on low-frequency noise in silicon PMOSFETs,” IEEE Trans. Electron Devices, Vol. 49, pp. 409-413, 2002.

[4-6] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko and Chenming Hu,

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Chapter 5

[5-1] A. van der Ziel, Noise in Solid State Devices and Circuits. New York: Wiley, 1986.

[5-2] Ali Hajimiri and Thomas H. Lee, “A general theory of phase noise in electrical oscillators” IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, 1998.

[5-3] K. K. Hung, P. K. Ko, C. Hu and Y. C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,” IEEE Trans. Electron Devices, vol. 37, pp. 654-665, 1990.

[5-4] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A physics-based MOSFET noise model for circuit simulators,” IEEE Trans. Electron Devices, vol. 37, pp.

1323-1333, 1990.

[5-5] M. H. Tsai and T. P. Ma, “1/f noise in hot-carrier damaged MOSFET’s: effects of oxide charge and interface traps,” IEEE Electron Device Lett., vol. 14, pp.

256-258, 1993.

[5-6] M. J. Knitel, P. H. Woerlee, A. J. Scholten and A. T. A. Zegers-Van Duijnhoven, “Impact of process scaling on 1/f noise in advanced CMOS technologies,” in IEDM Tech. Dig., pp. 463-466, 2000.

[5-7] Hisayo sasaki Momose, Hideki Kimijima, Shin-ichiro Ishizuka, Yasunori Miyahara, Tatsuya Ohguro, Takashi Yoshitomi, Eiji Morifuji, Shin-ichi Nakamura, Toyota Morimoto, Yasuhiro Katsumata and Hiroshi Iwai, “A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime,” in IEDM Tech. Dig., pp. 923-926, 1998.

Effect” Induced by Electron Valence Band Tunneling in Ultrathin Gate Oxide Bulk and SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 50, pp.

1675-1682, 2003.

[5-9] K. Kandiah, M. O. Deighton and F. B. Whiting, “A physical model for random telegraph signal currents in semiconductor devices,” J. Appl. Phys., vol. 66, pp. 937-948, 1989.

[5-10] Nuditha Vibhavie Amarasinghe and Zeynep Çelik-Butler, “Complex random telegraph signals in 0.06mm2 MDD n-MOSFETs,” Solid-State Electronics, vol. 44, pp. 1013-1019, 2000.

[5-11] Zeynep Çelik-Butler and Fang Wang, “Effects of quantization on random telegraph signals observed in deep-submicron MOSFETs,” Microelectronics Reliability, vol. 40, pp. 1823-1831, 2000.

[5-12] G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectronics Reliability, vol. 42, pp. 573-582, 2002.

[5-13] E. Simoen and C. Claeys, “Random Telegraph Signal: a local probe for single point defect studies in solid-state devices,” Materials Science and Engineering, vol. B91-92, pp. 136-143, 2002.

[5-14] R. Brederlow, W. Weber, D. S.-Landsiedel, and R. Thewes, “Fluctuations of the low frequency noise of MOS transistors and their modeling in analog and RF-circuits,” in IEDM Tech. Dig., pp. 923-926, 1999.

[5-15] C. W. Tsai, S. H. Gu, L. P. Chiang and Tahui Wang, “Valence-band tunneling enhanced hot carrier degradation in ultra-thin oxide nMOSFETs,” in IEDM Tech. Dig., pp. 139-142, 2000.

[5-16] Scott T. Martin, G. P. Li, Eugene Worley and Joe White, “The Gate Bias and Geometry Dependence of Random Telegraph Signal Amplitudes,” IEEE Trans. Electron Devices, vol. 18, pp. 444-446, 1997.

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姓名: 吳俊威 性別: 男

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