5.4.1 Abnormal Noise Characteristics in Frequency Domain
Fig. 5-2 shows the gate oxide thickness (tox) dependence of the normalized noise power spectrum density at f=100Hz. Due to a statistical nature of flicker noise, devices with too small area may exhibit a large fluctuation range in noise [5-14]. Therefore, the measured devices have a larger area (W/L=10µm/1µm) and each noise measurement data point represents an average of 5 devices. The noise is measured in the linear operation region (Vd=0.2V, Voverdrive=0.7V) to make sure the channel carrier distribution is uniform. As shown in Fig. 1, the SId/Id2 decreases as the gate oxide thickness reduces from 65Å to 22Å. This result agrees with the published unified flicker noise model [5-3,4] because oxide trap density is reduced in thinner oxides. However, as gate oxide thickness continuously scales down, the noise level exhibits an abnormal increase. Fig. 5-3 compares the temperature dependence of the 1/f noise in large area n-MOSFETs n-MOSFETs (W/L=10µm/1µm) with tox=15Å and 65Å. Strong temperature effect in the 15Å oxide device is observed.
The noise characteristic in a small area ultra-thin oxide n-MOSFET with a single trap time constant is first analyzed. Fig. 5-4 shows the measured and calculated noise power spectral density in a W/L=0.16µm/0.12µm n-MOSFET. The gate oxide thickness is 15Å. The noise has Lorentzian-like spectral distribution [5-15], characterized by a constant power spectral density at low frequencies and a roll-off with f-2 for high frequencies. The cut-off or
corner frequency (fc) corresponds to the 3-dB point of the spectrum and is related to the reciprocal characteristic time (t) of the underlying trap (fc=1/2πτ). The calculated result is based on the τ (1/τ=1/τH+1/τL) extracted from associated RTS (will be shown later) and is in good agreement with the measured power spectral density.
In order to investigate the excess noise source in the 14Å oxide n-MOSFETs, the temperature dependence of the noise characteristic in a small area device (W/L=0.36µm/0.12µm) with a single trap is analyzed. The measured noise exhibits a Lorentzian spectrum, as expected in a single trap device. Fig. 5-5 shows the temperature dependence of (SId/Id2)×frequency versus frequency. The temperature varies from 25°C to 125°C. Obviously, as temperature increases, the trap time constant decreases, resulting in a higher corner frequency. Based on the Shockley-Read-Hall (SRH) statistics, the capture time constant can be described by:
⎟ where ∆Eb is the energy barrier for the capture of an carrier and N is the carrier density. The linear behavior of the Arrhenius plot shown in Fig. 5-6 reveals that the source of the noise is related to interface trap assisted generation/recombination, which follows the SRH process.
Fig. 5-7 shows the gate voltage (Vg) dependence of fc. Obviously, there exist two groups of trap frequency (or two trap energy levels) with one (Et1) observed in weak inversion (Vg<0.9V) and the other (Et2) in strong inversion (Vg>1V). Furthermore, significant substrate current is noticed in the 15Å oxide device in strong inversion regime (Vg>1V) in Fig. 5-8 because valence band electron tunneling from the Si substrate to the poly-gate occurs and generated holes flow to the substrate [5-15].
Fig. 5-9 illustrates valence electron tunneling induced substrate current and interface trap energy levels.
5.4.2 Analysis of RTS Behavior in Time Domain
The gate bias dependence of corresponding RTS is then investigated. Fig. 5-10 shows typical RTS patterns in a small area (W/L=0.16µm/0.12µm) 15Å gate oxide n-MOSFET in weak inversion (Vg<0.9V). As can be seen, τL increases and τH decreases as Vg increases from 0.65V to 0.9V. Noticeably, RTS vanishes at Vg=0.9V. Fig. 5-11 shows the Vg dependence of average τL and τH (extracted from RTS). The τL and τH in weak inversion correspond to the electron emission and capture times at the interface trap Et1, as illustrated in Fig. 5-12(a). As Vg increases, τH decreases and τL increases because of a larger channel electron population and thus a smaller electron capture time. Our result here is consistent with the findings for thicker gate oxides in previous publications [5-9]. In contrast, Fig. 5-13 shows the RTS patterns in strong inversion from Vg=1.0V to 1.6V. The RTS is still undetectable at Vg=1V and re-appears for Vg>1V. Fig. 5-14 shows the Vg dependence of average τL and τH
extracted from the RTS. Interestingly, we find that the RTS patterns in strong inversion (Vg>1V) exhibit an opposite trend. The Vg dependence of τH and τL in strong inversion is opposite to that in weak inversion. It should be mentioned that other study [5-16] could also explain the observed RTS behavior based on the assumption of mobility fluctuation domination. However, the ∆Id/Id characteristic (mentioned in [5-16]) in our RTS results shows that the RTS behavior is still on the regime where number fluctuation dominates. The real cause of the inversed RTS behavior should be further studied.
5.4.3 Valence-Band Tunneling Induced Noise
In order to find out the opposite charge trapping and de-trapping behavior from weak inversion to strong inversion, the trap electron occupation factor (ft) is analyzed. The ft can be
evaluated as follows:
Fig. 5-15(a) shows ft versus Vg from weak inversion to strong inversion. In weak inversion regime (i.e., Vg<0.9V), ft increases with Vg because of an increased channel electron population. As ft increases to 1, RTS is undetectable since the trap is always occupied by an electron. In strong inversion regime (i.e., Vg>1V), ft declines from unity with increasing Vg.
This means, at a larger Vg, although the energy level of the interface trap is deeper with respect to the electron Fermi level, the chance of the trap being occupied by an electron becomes smaller. This result is quite different from the equilibrium case that ft should increase as the trap energy becomes more negative with respect to the Fermi level (see Eq. (2) where Et is the trap energy, Ef is the Fermi level). electrons always occupy the trap. However, the ft begins to decrease as valence band electron tunneling occurs (Vg>1V). Thus, the RTS re-appears and the SId/Id2 reaches another peak.
The possible explanation for the abnormal noise behavior in strong inversion is illustrated in Fig. 5-12(b). In strong inversion regime, a large Vg causes strong valence electron tunneling and leaves more holes behind in the channel. τH and τL then correspond to electron capture time and hole capture time respectively, as illustrated in Fig. 5-12(b).
Because of the increased channel hole concentration at a larger Vg, τL is smaller. The non-equilibrium carrier distribution also results in the splitting of electron and hole quasi
Fermi-levels. An interface trap (Et2) between the two quasi Fermi levels serves as the recombination center of electrons and holes. Thus, the local electron concentration in the vicinity of the trap is reduced and τH increases. The increase of τH and the decrease of τL lead to a reduced ft. The second peak of SId/Id2 in strong inversion condition (Vg>1V) in Fig.
5-15(b) therefore can be well explained.
For comparison, the ft and SId/Id2 versus Vg in a thicker gate oxide (33Å) n-MOSFET are also characterized. The result is shown in Fig. 8. The ft stays at unity in strong inversion.
Neither RTS nor the second noise peak is observed in strong inversion since valence-bane tunneling is insignificant in such thick gate oxide devices.
5.5 Summary
Low frequency flicker noise in analog n-MOSFETs with 15Å gate oxide is investigated.
A new noise generation mechanism resulting from valence band electron tunneling is proposed. In strong inversion condition, valence-band electron tunneling from Si substrate to poly-gate takes place and results in the splitting of electron and hole quasi Fermi-levels in the channel. The excess low frequency noise is attributed to electron and hole recombination at interface traps between the two quasi Fermi-levels. Random telegraph signal due to capture of channel electrons and holes is characterized in a small area device to support our model.
Fig. 5-1 (a) RTS in the drain current of an n-MOSFET
(W/L=0.32µm/0.12µm) measured at Vg=0.9V,Vd=0.2V. (b) The ∆Id can be extracted from the current interval between the two maximum number and the two peaks can be clearly symbolized as two-level RTS.
8.0x10-5 8.0x10-5 8.1x10-5 8.1x10-5
8.0x10-5 8.0x10-5 8.1x10-5 8.1x10-5 8.1x10-5 0