圖 5-14 為量測晶片的架構圖，首先我們會進行打線，接下來利用 HP 8113A 波 形產生器產生一156.25MHz 的輸入信號，E3610A 作為供電源，輸出部分則是利用 86100B 觀察晶片輸出的時脈抖動，並量測眼圖。
圖 5- 14 量測晶片的架構圖
第六章 結論
本論文利用可調變參考訊號相位注入震盪器，消除由相位雜訊所累積的時脈抖動，
並且利用不同的相位注入強度，使鎖相迴路輸出訊號在不同的環境中得到最佳的效能。
在數位控制震盪器設計方面，不同於一般設計解析度小於1ps 的架構，往往需要 10
位元以上的調整機制，在我們的架構中，利用7 位元的數位控制延遲單元，加上三角積
分調變器的操作，在不增加數位控制震盪器多餘硬體消耗的情況下，大大改善了解析度 的問題，使全數位鎖相迴路能應用於高頻操作，並且具有良好的輸出時脈抖動表現。
我們使用TSMC 0.13um RF 製程來實踐整個電路架構，並且對電路做佈局後模擬，
得到電路規格表。在供電壓1.2V 情況下，輸出頻率為 1.25GHZ，具有八個輸出相位，
輸出時脈抖動為17ps，消耗功率為 22mw。
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