In a modern life, we can find everywhere the novel of portable electronic products bringing the convenience and practicality for people. For instance, cellular phones, digital still camera, notebook, USB flash drive, iPod, and even gaming like PSP, etc [34]. The successes of all of them as mentioned above are attributed to the applications of memory technology. There are two typical types of memory: volatile and non-volatile. The former means a memory that requires power supply to maintain the stored information and data lose while the power is turned off. Instead, the latter has a capability to retain the storage data for a long time even without power supply.
Today, flash is the mainstream of the non-volatile memory technology [35-36]. The evolution of flash memory mainly can be classified into three types: floating gate (FG), Silicon/Oxide/Nitride/Oxide/Silicon (SONOS), and nano-crystal (NC) type in sequence.
In history the first FG non-volatile memory was published by D. Kahng and S.
M. Sze at Bell Labs in 1967 [37]. The stack-structure FG memory used a conductive layer as a charge stored layer, which is sandwiched between two insulated dielectrics.
The current FG memory device structure is shown in Fig.1-4. Despite the conventional FG memories have widely applications in non-volatile memory market share, they face some crucial constraints while the device is scaling down. First, the issue of reducing the operation voltage, it will degrade memory performance since the read and program/erase (P/E) speeds are related to the operation voltage. Second, much thinner tunneling oxide is required for continuous scaling the device structure.
Although the thinner tunneling oxide would speed up the operation speed, the retention characteristics of charges stored in FG may degrade severely. Thus there is a trade-off between reliability and speed for determining the tunneling oxide thickness.
Third, the quality of tunneling oxide degrades via tens of thousands of P/E cycles, generated defects form leaky path will result in the whole charges stored in the FG losing. It is because that conventional FG memory uses conductor as a charge trapped layer, as long as one leaky path generates, all of charges would leak through the path to the silicon substrate.
Therefore, in order to improve the way of charge storage, SONOS-type memory has been developed [38-39]. In 1967, Wegener et al. invented the first metal gate nitride memory device [40] with stack of Metal/Nitride/Oxide/Silicon (MNOS) structures. However, charges stored in the nitride trapping layer would leak to the top gate directly. Therefore a method to improve the retention was introduced the silicon dioxide as a blocking layer between the top gate and the nitride charge trapping layer.
The Oxide/Nitride/Oxide (ONO) gate dielectric stack is shown in Fig. 1-5. The basic charge storage mechanism of SONOS-type memory is storing charges in discrete traps of the silicon nitride layer. When defects are generated by several P/E operations in the tunneling oxide, only portion of charges which are proximal to the defect will lose. Hence, SONOS-type memories exhibit better retention characteristic with respect to the conventional FG memory and have other advantages such as good compatibility with standard CMOS process, lower operation voltage and power consumption, and the importance of scaling feasibility. Nevertheless, they still have some problems to be solved. First, erase can operate in the long pulse width only when the erase voltage is small. Once erase voltage is large, threshold voltage may saturates owing to the counteract of electron current tunneling through blocking layer and hole current tunneling through tunneling layer, which is called “erase saturation”
[41], is a poor characteristic for SONOS-type memories. Second, charges stored in the trapping layer may migrate to the nearest trapping nodes, called “charge migration”
[42]. It will lead to the change of memory characteristics. In addition, the disturbance
effect on SONOS memory cell array is also an issue that stored charges may transfer to the other memory cell due to the sharing of the same word-line or bit-line.
For the sake of further modifying these problems mentioned above, a novel structure of NC non-volatile memory has been proposed and is view as a good potentiality for next generation non-volatile memories. The main attraction is its charge stored mechanism. As shown in Fig. 1-6, every isolated nano-dot can store few electrons and each of them is surrounded by insulated dielectrics in the trapping layer.
Besides, the surrounding dielectric and nano-dots possess higher potential barrier to prevent stored electrons from escaping. Consequently, NC memories exhibit better retention characteristics than SONOS type memories. When leak paths are generated by defects, only few electrons stored in specific nano-dot which connects with leaky path will be lost while most of the others are remained. In addition, the disturbance effect can be eased up since the charge migration is suppressed by good isolation between any two nano-dots. Another advantage is the increasing of gate coupling effect when vertical electric field across nano-crystals, the work function of nano-crystals can be tuned to optimize the device performances by using variety of metal materials to form nano-crystals [43-45]. Due to these merits, the thickness of tunneling oxide in NC memories can be decreased without degrading the retention performance, and then the P/E speed and power consumption can be improved. For optimizing memory performances of the NC memory, higher density, uniform distribution and suitable size [46] of nano-crystal should be achieved.
1-4 Motivation
As mentioned in Section 1-1, EUVL is one of the most promising next generation lithography technologies for sub-22nm technology nodes. In the recently
years, many semiconductor manufacturing companies have installed full-field EUV lithography systems showing the possibility for substituting present lithography technology. However, the wavelength of EUV light is 13.5nm which is strongly absorbed in all materials. The relative energy is 91.8eV which is much higher than the chemical bonding energy in dielectrics and the band gap of gate dielectric layers.
Once MOS devices are exposed to EUV, such high energy radiation may cause some problems including the generation of electron-hole pairs in dielectric, interface states at dielectric/silicon interface, and traps or defects due to broken bonds in bulk dielectric. These phenomena will severely degrade the performance of electrical characteristic in MOS devices.
On the other hand, because EUVL can mass-produce IC chips by adapting mask sets, it is recognized more suitable for memory ICs rather than logic ICs. For this reason, the impact of EUV irradiation induced damages on the characteristics of memory devices being fabricated should be investigated. Although the EUV light is prone to be absorbed in all materials which is mentioned above, indicating that gate dielectric layers will not be damaged at the back-end-of-line process owing to the protection by gate electrodes and inter layer dielectrics. Nevertheless, if the protected layer is not thick enough, EUV will penetrate the gate electrode to damage the gate dielectrics at the back-end-of-line processed and of course at the front-end-of-line process.
Among non-volatile memories, SONOS and NC memories are two of the most promising candidates for next generation non-volatile memories. Therefore, they will face the lithography process with EUVL systems absolutely. Only when we investigated the degree of EUV radiation damage affected on the electrical characteristics of these memory devices, the improved methods for prevent from damaging can be achieved to confirm normal functionality of memory ICs after
process fabrication. Some literatures have been reported that the radiation damage on the FG [27-28, 47-48] and NC [28, 30-33] non-volatile memories with different radiation source such as X-ray, heavy ion, and protons. However, according to our knowledge, the EUV irradiation induced damage on the SONOS-type and NC non-volatile memories have not been reported.
In this work, we will investigate the radiation damage of EUV on advanced thin film transistor (TFT) -SONOS and multi-gate NC non-volatile memories with different dosage. After EUV irradiation, memory characteristic measurement such as memory window, P/E speed, charge retention, and endurance will be performed to observe the total dose dependent device damage. Besides, post-irradiation annealing will also be implemented to investigate whether the memory performances could be recover or not.