In order to identify the difference in the memory window characteristic before and after EUV irradiation, the basic characteristic of memory window of the fresh TFT-SONOS memory should be examined firstly to avoid mistaking some phenomena as the cause of EUV irradiation. Fig. 3-4 shows the program and erase windows of the TFT-SONOS memory experienced three times memory window measurements with pulse width of 1 s. The initial Vt is at Vg = 0V and FN tunneling is used for both program and erase operations. The P/E voltage pulses from Vg = ±8 V to V = ±18 V with a 2 V interval. It is clear that the values of V in the program state in
the range of Vg = 10V to Vg = 18V after P/E operations increase obviously with respect to the 1st operation. This phenomenon can be explained by the imperfect bonding in the Si3N4 CTL. The memory effect on SONOS is due to the charge trapping by the defects induced traps in the CTL. The residual hydrogen in the Si3N4
CTL may passivate some defects and then reduce the trap density. During P/E operations, the applied high voltages may break the hydrogen bonds and/or break the other bonds in the Si3N4 CTL and generate defects or traps as new charge storage sites, causing the increase of Vt shift in the program state. The third P/E operations exhibits even lager memory window but the generated trapping sites are gradually saturated and relatively stable. Fig. 3-5 compares the energy distribution of the trap density in the CTL after the 1st and 3rd times P/E operation. It is obvious that the trap density after three times P/E operations is much higher than that only performed one P/E operation, which proves that more defects or traps are generated during high-voltage P/E operations. The trap density is about 1x1011 - 2x1011 eV-1cm-2 after one P/E operation and about 5x1011 - 8x1011 eV-1cm-2 after three times P/E operation. Thus, to record the memory window characteristic before EUV irradiation, memory devices must receive P/E operations for at least three times in advance.
Fig. 3-6 shows the P/E windows of the TFT-SONOS memory before EUV irradiation, experienced 1 min EUV irradiation, and 264 hrs after EUV irradiation.
Some important phenomena are observed in Fig. 3-6. First, a slightly reduction of the initial Vt at Vg = 0V after EUV irradiation indicates that a small amount of the net positive charges are generated, which has been explained in section 3-2-1. Second, the Vt values in the program state at higher program voltage (14V ~ 18V) increase slightly, which implies a few new traps were generated during EUV irradiation. It is postulated that EUV has sufficient energy to break bonds in the dielectrics, causing some traps produced in the Si3N4 CTL. Third, the Vt values in the erase state show an
hump around Vg = ±10 V, which indicates the electron injection into the CTL is more easier than electron escape from traps. As the P/E voltage increases to Vg = ±18 V, the Vt in the erase state after EUV irradiation is higher than that before EUV irradiation.
This phenomenon is suspected to be due to the EUV induced damages in the blocking layer. For the SiO2 tunneling layer, the hole injection barrier is higher than the electron injection barrier, therefore, holes are relatively hard to tunnel through the SiO2 during erase operation. Meanwhile, electrons may tunnel through the blocking layer to the CTL. Thus, the damaged blocking layer results in electrons injection from the top gate much easier than holes injection from substrate during erase operation.
The P/E characteristic after 264 hrs room temperature storage after EUV irradiation is also shown in Fig. 3-6. It is observed that the memory device can be programmed to even higher Vt value with respect to that immediately after EUV irradiation. The reason is not clear yet but we suspect it may be due to the deviation in the measurement process since not all irradiated memory cells exhibit the same phenomenon. The Vt can be erased to lower level at high erase voltage (-18V), this improvement indicates that EUV radiation induced defects in the blocking layer can be repaired with time.
Similar but more pronounced phenomena such as net positive charge generation by EUV irradiation, higher Vt values in the program state, and erase saturation at high erase voltage are observed on the 2 min and 3 min EUV irradiated TFT-SONOS memories as shown in Fig. 3-7 and Fig. 3-8, respectively. An apparent reduction of the initial Vt at Vg = 0V implies that more positive charges are generated with respect to 1 min EUV irradiation since e-h pair generation is a dose-dependent process. The increase of program state Vt at higher program voltage (14V ~ 18V) shown in Fig. 3-7 indicates even more trapping sites are generated. Moreover, the increase of V in both program and erase states is observed in Fig. 3-8. It is suspected
that the 3 min EUV irradiation generates relatively deep-level traps and severely damaged blocking layer and results in hard-to-erase so that all the erase state Vt
values increase. The phenomenon of erase saturation is more pronounced in Fig. 3-7 and Fig. 3-8 than in Fig.3-6, which indicates that more defects are generated in the blocking layer during the longer EUV irradiation time.
The recover characteristics of memory window shown in Fig. 3-7 and Fig. 3-8 are slightly different from that shown in Fig. 3-6. The Vt values in both program and erase states after long term room temperature storage recover to the pre-irradiation values, which implies the EUV irradiation generated traps in the Si3N4 CTL are self-annealed with time.
In order to confirm our explanations on the observed phenomena, the energy distributions of the trap density in the CTL before and after EUV irradiation, and after long-term storage after EUV irradiation are extracted. The results are shown in Fig.
3-9. It is clear that the trap density after EUV irradiation increases approximately to 7x1011 - 1x1012 eV-1cm-2, which is higher than that before EUV irradiation. This result proves that new traps are indeed generated during EUV irradiation. After long-term storage, the trap density gradually recovers to the pre-irradiation value, which supports that the EUV irradiation produced traps can be self-annealed with time at room temperature.
3-2-3 P/E Speed
The program speed and erase speed of the TFT-SONOS memory are shown in Fig. 3-10 and Fig. 3-11, respectively. The gate pulse is +14V for program speed measurement and -18V for erase speed measurement. As expected, the program and erase speeds increase obviously with the increase of the magnitude of gate voltage.
The programmed Vt shift is larger than the erased Vt shift. That is why we chose
higher gate voltage for erase operation. A slightly increase of the Vt shift in both program state and erase state at the 2nd and 3rd times measurement is observed in Fig.
3-10 and Fig. 3-11, respectively. This phenomenon is consistent with that observed in Fig.3-4 and is explained by the imperfect bonding in the Si3N4 CTL. The difference between the 2nd and the 1st times measurement is more apparent for the 1s pulse width.
The P/E conditions with 1s pulse width are identical to those used in memory window characterization at Vg = 14V for program and Vg = -18V for erase in Fig. 3-4. It should be noted that new traps would be generated by high voltage and long pulse width P/E operations. After the 1st time P/E speed measurement, new traps are generated so that the Vt shifts at the 2nd time P/E speed measurement increases. After 2-3 times high voltage and long pulse width P/E operation, the trap density becomes stable.
Fig. 3-12 and Fig. 3-13 show the program speed and erase speed, respectively, of the TFT-SONOS memory before EUV irradiation, after 1 min EUV irradiation, and after 264 hrs room-temperature storage after EUV irradiation. The program speed increases after 1 min EUV irradiation, which implies that the EUV irradiation generates new traps in the Si3N4 CTL. Instead, the erase speed decreases slightly in the range of 1μs to 10ms and more seriously in the range of 0.1s ~ 1s, which indicates that the EUV irradiation degrades the blocking layer and causes electron backside injection, especially at long pulse width. Both phenomena are consistent with those observed in the memory window characterization on the device after 1 min EUV irradiation as shown in Fig. 3-6. After 264 hrs room-temperature storage, both program speed and erase speed recover. The recovery of erase speed at 1s pulse width implies that the EUV irradiation generated defects in the blocking layer can repair with time so that the effect of electron backside injection decreases. This phenomenon can also be seen in Fig. 3-6.
The program and erase speeds of the TFT-SONOS memories after 2 min EUV irradiation are shown in Fig. 3-14 and Fig. 3-15, respectively. It is clear that a 2 min EUV irradiation increases the program speed, which is similar to that observed in Fig.
3-12. The erase speed changes slightly as the erase pulse width is shorter than 0.1s.
Obvious erase saturation occurs at 1 sec pulse width. After 240 hrs room temperature storage, the program speed completely recovers to the pre-irradiation characteristic.
However, the erase saturation at 1 sec erase pulse width does not recover. These phenomena imply that the irradiation produced traps in the Si3N4 CTL recover with time but the defects in the blocking layer do not.
More pronounced but similar phenomena of the program and erase speeds are observed on the 3 min EUV irradiated TFT-SONOS memories as shown in Fig. 3-16 and Fig. 3-17, respectively. The overall program speed increases greatly which implied that more traps are generated during the 3 min EUV irradiation. This result is consistent with that shown in Fig. 3-12. The erase speed decreases obviously at short pulse width but slightly decreases at high pulse width. After 257-hrs room temperature storage, similarly, the program speed gradually recovered to the pre-irradiation characteristic. The erase speed at short pulse width increases apparently but decreases severely at long pulse width. This unique phenomenon is different from the other memory cell and need to be examined in the future work.