Measuring the endurance characteristic can learn some important information on the reliability of memory devices such as charge trapping uniformity and gate
dielectrics quality. For the former, charge non-uniform distribution generally occurs in one side injection case, for example, only drain-side or source-side injection.
Therefore, it is not a main issue in this thesis since FN tunneling is used for both program and erase operation. For the latter, memory device degrades during numerous of P/E cycles due to the deterioration of the tunneling oxide. Thus, endurance characteristic is prone to observe whether the EUV radiation damages the oxide quality or not.
Fig. 3-21 shows the endurance characteristic of the TFT-SONOS memory before EUV irradiation. The pulse condition is Vg = +17 V for program and Vg = -20 V for erase, both pulse widths are 10 msec. It is noted that all the memory cells in this part use the same pulse condition. Fig. 3-21 shows the memory windows of the device before EUV irradiation up to 105 P/E cycles. The 56% degradation of memory window means the endurance performance of our memory devices is not good enough.
In order to clarify what mechanism resulting in degradation, the Id-Vg curves before and after endurance test are shown in Fig. 3-22. In the 1st P/E cycle, the subthreshold swing (SS) in the program state is poorer than that in the erase state. Since the program operation is performed in advance of erase operation, the better SS in erase state indicates that the SS degradation in the program state is not due to increase of the interface state. This phenomenon can be attributed to the surface roughness of the poly-Si channel. The rough interface between poly-Si channel and tunneling oxide will cause non-uniform electric field for FN tunneling and leads to SS degradation because of non-uniformly stored charges. After 105 P/E cycles, the SS in both program and erase states degrades furthermore. Since the SS in program state is very close to that in erase state, the degradation mechanism is also attributed to the non-uniform charge storage. The narrowing of the memory window after repeated P/E operations may result from the degradation of the blocking layer so that back side
injection from control gate occurs in both P/E operations.
After EUV irradiation, much worse endurance characteristic is observed on the 1 min EUV irradiated TFT-SONOS memory, especially in the erase state, as shown in Fig. 3-23. The Vt value of erase state increases after 105 P/E cycles, which is mainly attributed to the damaged blocking layer. As mentioned in the previous discussion, defects are generated in the blocking layer by EUV radiation and it will accelerate the degradation of blocking layer after numerous high-voltage P/E operations. Thus, electron backside injection enhanced and results in a large increase of the Vt in the erase state. The memory window shows 83% degradation which is relatively worse than the non-irradiated memory cell. In addition, we can also verify our explanation from the Id-Vg curves which is shown in Fig. 3-24. Despite the memory window shrinks due to the SS degradation, an apparent Vt shift of erase state implied the enhanced electron backside injection due to EUV damaged blocking layer.
Similar but more pronounced phenomena can be also found on the memory cells experienced 2 min and 3 min EUV irradiation as shown in Fig.3-25 and Fig.3-26, respectively. The memory window shows 87% degradation in Fig. 3-25 and 90%
degradation in Fig. 3-26 after 105 P/E cycles. The Vt value in the erase state after 104 P/E cycles increases obviously in Fig. 3-26, which implies longer EUV irradiation time generated more defects and causes even worse endurance characteristic. The Id-Vg curves of the endurance characteristic after 2 min and 3 min EUV irradiation are shown in Fig. 3-27 and Fig. 3-28, respectively. Strong electron backside injection can be observed in the erase state due to longer irradiation time.
From the above experimental results, it is clearly that the SONOS memory cell would be damaged by EUV irradiation. If the damaged memory cells can be recovered through the typical thermal budget in the back-end-of-line process, then it is not necessary to worry about the EUV irradiation induced damages. Otherwise,
careful process design and/or additional thermal budget must be employed. The process temperature in the back-end-of-line process is generally lower than 500C.
Fig.3-29 and Fig.3-30 shows the endurance characteristic of the 30 min EUV irradiated TFT-SONOS memory before and after 600C post-irradiation annealing, respectively. After 30 min EUV irradiation, the memory window shows 93%
degradation and the erase state degrades severely. The 600C post-irradiation annealing can improve the endurance characteristic partially, however, the memory window still shows a 63% degradation. It is concluded that the endurance degradation cannot be recovered by a 600C annealing.
Finally, the retention characteristic of memory cells which have been experienced endurance test is discussed. Fig. 3-31 shows the retention characteristic of the TFT-SONOS memory after endurance test. It is clear that the Vt values in the erase state cannot be as low as that before endurance test since the blocking layer has been degraded after numerous of P/E operations and then results in strong electron backside injection. The Vt values in the program state is higher than that after endurance test since the lower pulse voltage and longer pulse width are used to increase the Vt value so that the larger memory window is obtained. In addition, the retention performance in the erase state is worse than that of the device before endurance test and it shows a monotonic increase of Vt during the storage period. We try to explain this special phenomenon by the trapping of the backside injected electrons in the blocking layer. During the erase operation, the strong electron backside injection occurs and some electrons are trapped in the blocking layer, meanwhile, holes from channel are injected into the CTL. Thus, the trapped hole may tunnel through the thin tunneling layer during storage. However, it is relatively harder for the trapped electron in the blocking layer to escape because the blocking layer is rather thick. In this case, the Vt values in the erase state increases with the storage
time instead of decreasing. In addition, the retention performance in the program state is also worse than that of the device before endurance test, which indicates the tunneling layer is degraded after numerous of P/E operations. This can also support the detrapping of holes in the erase state. This memory cell exhibits about 50%
window loss after 105 seconds.
In addition, the retention characteristics of the TFT-SONOS memory after endurance test with different EUV irradiation time are shown in Fig. 3-32 to Fig. 3-34.
The retention performances are even worse after EUV irradiation. Almost all the irradiated memory cells exhibit more than 60% window loss after 105 seconds. It can be observed that the retention performance in the program state is worse than that of the device before endurance test as shown in Fig. 3-31, which supports that the tunneling layer is damaged by the EUV irradiation again.