Figure 2-2 illustrates the effect of forming gas anneal (FGA) on 100 μm2 p+ n diodes with
different activation conditions. (a) 500℃ and (b) 550℃. The activations were done for 30s.
We find that the forward current density in our cases is lower than others had been reported
[13]. We think the cause of lower forward current is the lower bulk doping level. The lower
bulk doping level leads the higher series resistance and reduces the forward current. And the
lower bulk doping level also brings out the higher reverse leakage current. Because the lower
bulk doping level causes the huge bulk generation current such that the higher leakage current
in our samples. From (a), we find that the reverse current of the p+ n diode after 300℃ FGA is
smaller than non-FGA sample while forward current is almost equivalent to others. While the
FGA temperature is larger than 300℃ (350 and 400℃), the reverse current is increased
immediately. Specially, the reverse current of 400℃ FGA is one order than non- FGA sample
at Vjunc.=-1V. We can see the analogous effect from Fig 2-2 (b). Figure 2-3 illustrates the
reverse current density at Vjunc
=
-1V with different FGA conditions. As we have mentioned,the reverse current density are increased after higher FGA temperature (>300℃). The reverse
current after 300℃ FGA is reduced because of the decrease of the defects. Forming gas
annealing ambient is H2 and N2. Hydrogen (H2) is confirmed to passivate the defects such that
the reverse current reduced. The reason for the increasing reverse current after higher FGA
temperature (>300℃) is that Ge out-diffusion and Al incorporation in Ge bulk introduce
defects near the p+ n junction. Figure 2-4 is published on 2008 Electrochem. Solid-State Lette.
from IMEC and ASM Belgium [14]. It shows that the temperature >300℃, large-scale Ge
voiding and germanide overgrowth occur because of the out-diffusion of Ge. Figure 2-5 and
2-6 are the channel length dependent Id-Vg and Id-Vd electrical characteristics of the 500℃
activated Ge PMOSFETs with different FGA temperatures, respectively. Id-Vg characteristic
of the Al2O3 PMOSFETs with 500℃ activation for three different FGA temperatures is shown
in Figure 2-7. It shows some interesting events in Figure 2-7. First, Ioff current is decreased
after 300℃ FGA compared to non- FGA sample. However, Ioff current is increased after
higher FGA temperature (400℃) compared to non- FGA sample and 300℃ FGA sample.
Second, the 300℃ FGA sample has the steeper slop when Vd is small. Finally, we can find
that forming gas annealing shifts the curves of Id-Vg. We explain the results in order. The
reduction of Ioff current after 300℃ FGA is attributed to H2 passivates the interface state
density (Dit: 7.53x1011 eV-1cm-2 after 300℃ FGA vs. 1.07x1012 eV-1cm-2 before) and improve
the p+ n junction. But the higher temperature (400℃) introduces Ge out-diffusion in p+ n
junction such that Ioff current is increased. The steeper slope of Id-Vg curve after 300℃ FGA is
attributed to the lower Dit. Finally, the shift of the Id-Vg curve is attributed to threshold voltage
shift. Id-Vd characteristics of the Al2O3 PMOSFETs with 500℃ activation for three different
FGA temperatures are shown in Figure 2-8.
Based on the first order current-voltage approximation, the drive current ID for a MOSFET
in the saturation region can be written as below
(1.1)
Where Cox is the gate oxide capacitance and mainly determined by the permittivity and the
thickness of the gate insulator. μn is the mobility for the electrons or holes. W and L are the
channel width and length, respectively. VGS is the applied gate-to-source voltage, and VT is
the threshold voltage. From the above equation, the drain current Id is affected by Cox and μn.
The higher drain current Id after FGA is illustrated in Figure 2-8. We mainly attribute the
higher drain current Id to higher mobility and increasing Cox. However, the higher mobility is
attributed to the lower Dit and the lower S/D series resistance. The effective mobility of the Ge
PMOSFETs with different FGA temperatures are illustrated in Figure 2-9(a). References with
HfO2/Ge (SP and SN) [15] and Ge/Si after PMA (H2) [16] are compared with our data are
illustrated in Figure 2-9(b). The extracted effective hole mobility of the MOSFETs equation is
mentioned as below:
Where Qn= Cox (VGS-VT) and the drain conductance gd is defined as
(1.2)
Cox is obtained by C-V measurement for Ge PMOSFET at f (frequency)=10 kHz and gd is
obtained by Id-Vg at Vd=-50 mV. From Figure 2-9(a), we find that the mobility after FGA is
larger than non-FGA. Specially, the mobility after 400℃ FGA is almost 2 times than
non-FGA in all electric field. We can find that our device characteristics are not bad in
comparison with others in Figure 2-9(b). However, the Cox is higher after FGA is showed in
Figure 2-10. We consider that mobility is affected by Cox in our work. Id-Vg and Id-Vd
characteristics are shown in Figure 2-11 and 2-12, respectively. In Figure 2-11 and 2-12, it
shows the similar subthreshold slope and drive current except Ioff current for 500 and 550℃
samples. Ioff current at 550 ℃ sample is larger than 500℃ sample 1.6 times while Vg is
negative. Figure 2-13 shows Vth characteristics of the Al2O3 Ge PMOSFETs with different
FGA and activation temperatures. The continuing positive shift of Vth is related to Ge
out-diffusion [17], [18], [19]. Two possible incorporation mechanism: (a) out-diffusion of
gaseous GeO species from the substrate and downward into the high-k layer through airborne
transportation and (b) GeO volatilization from the IL and top surface of the Ge substrate [19].
The incorporation mechanism possibly causes VFB shift by inducing negative fixed charges
near the interface and into the dielectric.
(1.3)
(1.4)
Where Rch is channel resistance and RSD is source drain (S/D) series resistance. Figure 2-14
shows the Rm-Lg curves for extraction of RSD and ΔL. (a), (b), and (c) are different FGA
temperatures at 500℃ activation. (d) is 300℃ FGA with 550℃ activation. We find that the
S/D series resistance is reduced after FGA. The S/D series resistance of as-deposited sample
is 194Ω and 400℃ is 123Ω. The decreasing S/D series resistance attributes to higher
temperature improves the interface between the Ge substrate and metal pads by the formation
of alloy. However, the reducing S/D series resistance improves the drive current (ID) and
effective mobility (μeff) as mentioned previously. It is illustrated in Figure 2-15 that the
extraction of RSD and ΔL with different FGA conditions at 500 and 550℃. Figure 2-16 (a),(b)
show Dit calculated from the Conductance and Charge pumping method, respectively. We can
find the similar trend from the two figures. After 300℃ FGA, Dit is reduced slightly and Dit is
increased after higher FGA temperature. It means that 300℃ FGA indeed improve the
interface between the substrate and the gate insulator by H2 and higher FGA temperature
(≧400℃) degrade the interface. Figure 2-17 shows charge pumping current v.s Vg with
different FGA temperatures was evaluated at f =1MHz. We also find that the Icp current is
decreased after FGA treatment in comparison with as-deposited sample. Figure 2-18 (a)
shows the on/off ratio of Ge PMOSFETs with different FGA and activation temperatures. Ion
and Ioff are extracted at Vth+0.8V and Vth-4V, respectively. The 300℃ FGA sample have
higher value at on/off ratio about 103. However, the 400℃ FGA samples have the higher drive
current than others. As a result of the junction leakage, it degrades the on/off ratio. From
Figure 2-18 (b), the minimum of sub-threshold slope of Ge PMOSFET is 300℃ FGA sample
because of the minimum of Dit.
BTI is an important reliability issue of high-k gate dielectrics on silicon. Consequently, it
is necessary to evaluate the BTI property of the high-k gate dielectrics on germanium. It is
measured in MOSFETs biased under inversion. A negative voltage (Vstress) was applied to the
gate of a device, while the S/D and the substrate were grounded. Id-Vg and Id-Vd measurement
were conducted during the stress intervals. The measurement time between the two
consecutive stresses was ensured to be minimal in order to reduce the possible de-trapping of
the oxide trapped charge. Figure 2-19 show the NBTI degradation of Id degradation [Figure
2-19 (a)] and Gm degradation [Figure 2-19 (b)] by stress for Ge PMOSFETs. It should be
noted that non-FGA samples are subjected to severer the Id and Gm degradations. Figure 2-20
show the NBTI degradation of Vth shift [Figure 2-20 (a)] and SS degradation [Figure 2-20 (b)]
by stress for Ge PMOSFETs. It also represents that non-FGA samples have a higher Vth shift
and SS increase in comparison with FGA samples. It means that non-FGA samples are
subjected to NBTI degradation involves interface-trap generation. By employing FGA, Ge
PMOSFETs show almost no change in sub-threshold swing. It suggests that the immunity
from interface-trap degradation of Ge PMOSFETs could be achieved.
2-4 Summary
We already demonstrated a Ge bulk PMOSFETs by the standard 4 mask process. Most
important parameters such as Id-Vg, Id-Vd, effective mobility, Vth, sub-threshold swing and so
on are showed in this chapter. To further ensure the FGA technique can improve the interface
between the Ge substrate and gate dielectric, we employed NBTI. It showed that 300℃ FGA
can improve slightly the interface between Ge bulk and Al2O3 gate dielectric by lowering Dit.
After 300℃ FGA, the S/D series resistance also reduced from 194 Ω to 181 Ω. Since the
improvements of the interface quality and S/D contact, the drive current the mobility
increased. But the higher temperature FGA (>300℃) introduced the Ge out-diffusion such
that the junction leakage current increased. Although the junction leakage current increased,
the S/D series resistance decreased significantly and the interface state density (Dit) increased
slightly. After 400℃ FGA, it showed the highest mobility in comparison with others in our
work. Stressing at Vg=-3.2 or -3V, it showed that FGA samples had smaller Vth shift, Id and
Gm degradation and change of sub-threshold swing compared with non-FGA samples.
Dilute HF(HF:H2O=1:30,5 mins) and D.I. water 10 mins
PECVD deposit Field Oxide (thickness~4200 A)
Define the S/D region(1stMask)
Implantation(B+,60KeV,1e15cm-2)
Dopant activation (550℃,550 ℃)
Active area opening (2nd Mask)
ALD Al2O3deposition (~170 ℃)
Contact hole opening (3rdMask)
Al metallization (thermal coater)
Define metal pads (4thMask)
Ge substrate FOX
P-N junction
Al2O3 film
Al
Al Al
FOX FOX
Forming gas annealing (~5% H2,95% N2;30 mins)
Fig. 2-1 MOSFET fabrication flow chart.
Fig. 2-2 Effect of forming gas anneal (FGA) on 100 μm
2p
+n diodes with different activations (a) 500℃ and (b) 550℃. The activations are done for 30s.
Ge p-MOSFET
Fig. 2-3 Reverse current density at V
junc= -1V with different FGA conditions.