The measurement of junction leakage is 2.5nm Si capping layer

Boron, 1E15cm^-2, 10keV 700^oC, 30s

Fig. 3-9 Effects of thermal budget on junction leakage current at V

=-1V. The measurement of junction leakage is 2.5nm Si capping layer.

Fig. 3-10(a) P

N diode was implanted by Boron with 20keV energy and 3x10

cm

dose and annealing at 500

C 5 minutes. Reverse leakage current was divided by different area.

I R(μA)

Boron, 3E15cm^-2, 20keV 500^oC, 5mins

Fig. 3-10(b) P

N diode was implanted by Boron with 20keV energy and 3x10

cm

dose and annealing at 500

C 5 minutes. Reverse leakage current was divided by different perimeter.

Fig. 3-11(a) P

N diode was implanted by Boron with 20keV energy and 3x10

cm

dose and annealing at 500

C 10 minutes. Reverse leakage current was divided by different area.

Boron, 3E15cm^-2, 20keV 500^oC, 5mins

Boron, 3E15cm^-2, 20keV 500^oC, 10mins

Fig. 3-11(b) P

N diode was implanted by Boron with 20keV energy and 3x10

cm

dose and annealing at 500

C 10 minutes. Reverse leakage current was divided by different perimeter.

Fig. 3-12(a) P

N diode was implanted by Boron with 20keV energy and 3x10

cm

dose and annealing at 600

C 2 minutes. Reverse leakage current was divided by different area.

Boron, 3E15cm^-2, 20keV 500^oC, 10mins

Boron, 3E15cm^-2, 20keV 600^oC, 2mins

Fig. 3-12(b) P

N diode was implanted by Boron with 20keV energy and 3x10

cm

dose and annealing at 600

C 2 minutes. Reverse leakage current was divided by different perimeter.

Fig. 3-13(a) Effects of thermal budget on peripheral leakage current (J

) at V

=-1V. The measurement of junction leakage is 2.5nm Si capping layer.

Boron, 3E15cm^-2, 20keV 600^oC, 2mins

500C 30s 500C 2mins 600C 30s 700C 30s J p(A/cm)

Fig. 3-13(b) Effects of thermal budget on peripheral leakage current (J

) at V

=-1V. The measurement of junction leakage is 5nm Si capping layer.

black: 1e15cm^-2 red: 3e15cm^-2

annealing conditions

500C 5mins 500C 10mins 600C 2mins

J p(A/cm)

10^-4 10^-3 10^-2

closed: 20keV open: 40keV

Si cap: 5 nm

Chapter 4 Conclusions

4-1 Conclusions

Ge PMOSFETs

In this thesis, we presented two different substrate materials. One is the bulk Ge (n-type),

the other is epitaxial Ge channel on Si substrate by UHVCVD. At the beginning, we used gate

last process to fabricate Ge PMOSFETs. Then, we measured the electrical properties by

Agilent 4284 LCR meter and Keithley 4200 semiconductor characterization. We found the

mobility of our device is less than Si universality. In order to improvement of our devices, we

employed forming gas anneal (FGA) to improve the electrical properties. It has been reported

that high temperature FGA could improve the carrier mobility in Si and Ge. As a result of Ge

out-diffusion during higher temperature (>400^oC), we decided to employed the lower

temperature forming gas anneal (<400^oC) to improve the interface quality between the Ge

substrate and high-k Al2O3 dielectric. The reverse current of p+ n junction would be reduced

after 300^oC FGA. Because hydrogen would passivate the defects near the surface such that the

reduction of leakage current. But the leakage current would increase immediately after higher

temperature (>400^oC). As a result of the formation of pits or voids near the surface and fast

diffusion of Al into Ge bulk, these generated defects so that the leakage current increased.

Hence, 300^oC FGA device had the lower leakage current, subthershold swing, and interface

state density (Dit). But the effective mobility after 300^oC FGA just had a little improvement

compared with as-deposited samples. However, 400^oC FGA samples had the larger leakage

current, subthreshold swing, and interface state density (Dit). But 400^oC FGA samples had

largest mobility in our work. It had 2 times in comparison with as-deposited samples. Finally,

we used CVS to evaluate the quality of dielectric. We found that samples after FGA had better

quality in comparison with as-deposited.

Si_1-xGe_x/Ge/Si p⁺-n junction

We already utilized the epitaxial substrate materials to fabricate the pn junction. From the

electrical analysis, we found that peripheral leakage current dominated the reverse leakage

current with 2.5 and 5nm Si capping layers. And we thought the defects in Si capping layer

attributed to peripheral current. Since, 500^oC~700^oC could not repair defects from

implantation. However, higher annealing temperatures were not good for Ge channel. Hence,

we could deposit the thinner Si (<1 nm) capping layer top of Ge channel. Because, the thinner

Si layer can be consume in continuous processes and Si capping layer can be the passivation

layer to passivate Ge surface to gain the better interface quality.

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