Table 2-1 shows the conditions of implantation and annealing for 2.5nm Si capping layer.
Note that we didn’t have the device about 600oC 40keV. And Table 2-2 shows the conditions
of implantation and annealing for 5 nm Si capping layer. Note that we used two different
dosages in case of 5nm Si capping layer. Then, we show an equation [20] about the leakage
current and a simple diagram about the path of the leakage current in Figure 3-3. We could
divide the leakage current into two items. One is area leakage current, the other is perimeter
leakage current. First, we discussed 2.5nm Si capping layer at different annealing conditions
and we only chose 10keV to discuss. Figure 3-4(a) shows pn diode is implanted by Boron
with 10keV energy and 1x1015cm-2 dose and annealing at 500oC 30s. Reverse leakage current
is divided by different area. We find that the reverse leakage current at different area are not
closed. Figure 3-4(b) shows the same conditions of annealing and implantation except the pn
junction is divided by different perimeter. We find that the junction current is divided by
different perimeter are closed in comparison with area. Consequently, we think the peripheral
junction current dominates the junction leakage. Figure 3-5(a) shows p+ n diode was
implanted by Boron with 10keV energy and 1x1015cm-2 dose and annealing at 500oC 2
minutes. Reverse leakage current was divided by different area. The result of junction leakage
was like Figure 3-4(a). And Fig. 3-5(b) shows p+ n diode was implanted by Boron with 10keV
energy and 1x1015cm-2 dose and annealing at 500oC 2 minutes. Reverse leakage current was
divided by different perimeter. We found that the junction current was divided by perimeter is
closed compared with area. It meant that the junction leakage is dominated by peripheral
leakage current. We also found the same result in Figure 3-6(a) and Figure 3-6(b). Finally, we
showed the p+ n junction is annealing at 700oC activation in Figure 3-7(a) and (b). The result
of junction leakage, which one is dominated, peripheral junction leakage dominated the
junction leakage. Then, we took all conditions into comparison in Figure 3-8. We found some
interesting things. First, the peripheral leakage wasn’t affect by implantation energy. Second,
the peripheral leakage current was mainly affected by annealing temperature. The leakage
current was reduced almost 10 times after 700oC annealing compared with 500oC activation.
Hence, we though that the domination of peripheral leakage current is the defects. Because,
500oC~700oC annealing temperatures on Si couldn’t repair the defects by implantation. The
main source of junction leakage came from these un-repair defects. Figure 3-9 shows the
leakage current at different thermal budget. The main effect of leakage current is still
annealing temperature. Then, we discussed the electrical properties of the p+ n diode with
5nm Si capping layer. Since, we had two different dosages 1x1015, 3x1015 cm-2. But, we
found that the exhibit of 1x1015 cm-2 with 2.5nm Si capping layer is same as 5nm Si capping
layer. Here, we only discussed the result of 3x1015 cm-2 with 5nm Si capping layer. Figures
3-10(a) and (b) show p+ n diode were implanted by Boron with 20keV energy and 3x1015cm-2
dose and annealing at 500oC 5 minutes. Reverse leakage current was divided by different area
and perimeter, respectively. We found that the similar result with 5nm Si capping layer. The
reverse leakage current was dominated by peripheral current. Because, the reverse leakage
currents were divided by different perimeters, where are more closely than different areas.
Figures 3-11(a) and (b) show p+ n diode were implanted by Boron with 20keV energy and
3x1015cm-2 dose and annealing at 500oC 10 minutes. Reverse leakage current was divided by
different area and perimeter, respectively. We also found the same condition in comparison
with 500oC 5 minutes case. Figures 3-12(a) and (b) show p+ n diode were implanted by Boron
with 20keV energy and 3x1015cm-2 dose and annealing at 600oC 2 minutes. Reverse leakage
current was divided by different area and perimeter, respectively. Again, we found the similar
result at annealing 600oC 2 minutes. Consequently, we thought the defects from implantation
would not be able to repair in continuous annealing led to high reverse leakage current.
Figures 3-13(a), (b) show the effect of thermal budget on peripheral leakage current (Jp) at
VR=-1V. The measurement of junction leakage is 2.5 and 5nm Si capping layer, respectively.
We found that the peripheral leakage current was similar to each other in the range of
10-3~10-2 (A/cm). But, the time of annealing with 5nm Si capping layer is longer than 2.5nm
Si capping layer. Hence, we thought the thinner Si capping layer is better for Si/Ge/Si1-xGex
substrate material.
3-4 Summary
We had shown the electrical properties with different Si capping layer thickness and
thermal budget. From the electrical analysis, we found that peripheral leakage current
dominated the reverse leakage current with 2.5 and 5nm Si capping layers. And we thought
the defects in Si capping layer attributed to peripheral current. Since, 500oC~700oC could not
repair defects from implantation. However, higher annealing temperatures ware not good for
Ge channel. Hence, we could deposit the thinner Si (<1 nm) capping layer top of Ge channel.
Because, the thinner Si layer can be consume in continuous processes and Si capping layer
can be the passivation layer to passivate Ge surface to gain the better interface quality.
Wafer cleaning (DHF)
PECVD Field Oxide (thickness~4200 A)
Define implant region (1stMask)
Implantation(B+,10~40KeV)
Activation (500℃,600,700 ℃)
Back contact (Al)
Forming gas annealing (~5% H2,95% N2;30 mins)
Metal pads (Al)
Al FOX Al
Si substrate
epi-SiGe: 40nm epi-Si: 2.5 or 5 nm
epi-Ge: 7 nm
Fig. 3-1 P
+-N junc. fabrication flow chart
Fig. 3-2 TEM image of the capacitor cross section with SiH
4pretreatment. The bright layer is Al
2O
3. And under the Al
2O
3is Si interlayer.
Al2O3
Si interlayer
Ge substrate
Table 3-1 Conditions of implantation and annealing for 2.5 nm Si capping layer.
SiGe/Ge/Si(40/7/5)nm 500oC
5 mins
Table 3-2 Conditions of implantation and annealing for 5 nm Si capping layer.
B E A D
Fig. 3-3 The leakage current equation and a simple diagram about the path of leakage current.
Fig. 3-4(a) This pn diode was implanted by Boron with 10keV energy and 1x10
15cm
-2dose and annealing at 500
oC 30s. Reverse leakage current was divided by different area.
Boron, 1E15cm-2, 10keV 500oC, 30s
Fig. 3-4(b) This pn diode was implanted by Boron with 10keV energy and 1x10
15cm
-2dose and annealing at 500
oC 30s. Reverse leakage current was divided by different perimeter.
Fig. 3-5(a) P
+N diode was implanted by Boron with 10keV energy and 1x10
15cm
-2dose and annealing at 500
oC 2 minutes. Reverse leakage current was divided by different area.
Boron, 1E15cm-2, 10keV 500oC, 30s
Boron, 1E15cm-2, 10keV 500oC, 2mins
Fig. 3-5(b) P
+N diode was implanted by Boron with 10keV energy and 1x10
15cm
-2dose and annealing at 500
oC 2 minutes. Reverse leakage current was divided by different perimeter.
Fig. 3-6(a) P
+N diode was implanted by Boron with 10keV energy and 1x10
15cm
-2dose and annealing at 600
oC 30s. Reverse leakage current was divided by different area.
Boron, 1E15cm-2, 10keV 500oC, 2mins
Boron, 1E15cm-2, 10keV 600oC, 30s
Fig. 3-6(b) P
+N diode was implanted by Boron with 10keV energy and 1x10
15cm
-2dose and annealing at 600
oC 2 minutes. Reverse leakage current was divided by different perimeter.
Fig. 3-7(a) P
+N diode was implanted by Boron with 10keV energy and 1x10
15cm
-2dose and annealing at 700
oC 30s. Reverse leakage current was divided by different area.
Boron, 1E15cm-2, 10keV 600oC, 30s
Boron, 1E15cm-2, 10keV 700oC, 30s
Fig. 3-7(b) P
+N diode was implanted by Boron with 10keV energy and 1x10
15cm
-2dose and annealing at 700
oC 2 minutes. Reverse leakage current was divided by different perimeter.
VR= -1V
annealing conditions
500C 30s 500C 2mins 600C 30s 700C 30s
J p(A/cm)