Recently, the poly-Si thin film transistors fabricated by low-temperature process have received extensive study for their important applications to the active matrix liquid crystal display (AMLCD)[30][31]. To optimize the design of the poly-Si NW TFTs with high performance, it is important to develop a reliable analytical methodology based on the physical mechanisms that correlates the electrical characteristics with the fabrication condition. The performance of poly-Si TFTs is dominated by trapping states at grain boundaries and within the grains themselves [32][33]. Although the electron and hole field-effect mobility of poly-Si are considerably higher than those of α-Si, the values are still much lower than those of single-crystal silicon. Fig.3-1 shows the comparison of transfer property between sample(1) and sample(2). Sample(2) has smaller off-state leakage current, larger on-current , and better subthreshlod swing than Sample(1). Figure 3-2 shows the comparison of transfer characteristics between devices with 30 and 40 seconds over-etching time, both with the same gate height (100nm) and channel layer deposition thickness (100nm).
However, the device with 40 seconds over-etching 40 time depicts larger off-state leakage current, smaller threshold voltage, and better subthreshlod swing than the device with 30 seconds over-etching time. It is worthy to note that the off-state leakage current of the device with 40s over-etching is larger than that with 30s over-etching. We believe this is because the nano-wire channel with longer-etching time suffered from more plasma damage during the channel-etching step. The mechanisms of off-state leakage current will be discussed in section
3-3. In addition, we also observed that both thinner channel layer and shorter over etching-time affect the characteristics of devices. The comparison on characteristics between the device with 20s over-etching and the device with 25s over-etching, both having the same gate height (100 nm) and channel layer thickness (50 nm), is shown in Fig. 3-3. The comparison on characteristics between the device with 20s over-etching and the device with 25s over-etching, both having the same gate height (100nm) and channel layer thickness (50nm) is shown in Fig. 3-3. The comparison on characteristics between devices with 54nm and 30nm nano-wire thickness is shown in Fig. 3-4. It shows the device with thinner nanowire has smaller threshold voltage and higher drain current, indicating better gate control ability.
Detailed summary of characteristic parameters (VD=0.5V) with various channel layer thickness and etching times is shown in Table 3-1.
The transfer characteristics of SPC-before-etching and SPC-after-etching nano-wire devices are shown and compared in Figs. 3-5(a) and (b). The two figures indicate that the devices with SPC-before-etching nano-wire have better electrical properties. For the device with SPC-after-channel-etching, α-Si was re-crystallized in a confined space, and the grain growth would be easily impeded. As a result, the grain size is smaller than that in the device with SPC before channel etching. The comparison between n-channel and p-channel devices is shown in Fig. 3-6. The characteristics of the n-channel devices are better than that of the p-channel devices, owing to higher electron mobility. The results also indicate that more attentions need to be paid to optimize p-channel devices. Fig. 3-7 shows the threshold voltage of the devices with measurement deviation versus channel length. We can see the process uniformity of poly-Si NW TFTs is less than optimum, and is worse with shorter channel. This is owing to the difficulty in grain size and nanowire dimension control. Fig. 3-8 shows the on-current versus channel length at VG=10V, VD=0.5V. The results in Fig.3-8 basically agree with equation (2-1).
Another very important electrical characteristic of poly-Si TFTs is ID-VD output characteristic. The kink effect observed in the drain current of poly-Si TFT operating in the high drain bias regime has been investigated by several works [35-39]. With the aid of two-dimensional (2-D) numerical simulation, the nature of the kink effect had been identified to be due to the impact-ionization mechanism in the high field regime near the drain for the intrinsic poly-Si TFT [35-38]. Along the channel, the formation of the potential barrier of the grain boundary and defects cause the low transconductance and high threshold voltage of poly-Si TFTs. The barrier height is expressed in terms of channel doping, gate oxide thickness, grain size, and external gate as well as drain biases. Drain bias will result in an asymmetric potential barrier and introduce more carrier injection from the lowered barrier side. It is shown that this consideration is very important to characterize the saturation region under high drain bias condition.
Fig. 3-9 and Fig. 3-10 show the ID-VD output characteristics of n-channel devices with short channel and long channel, respectively. In Fig. 3-9 and Fig. 3-10, the short channel devices exhibit more significant kink effect than long channel devices in the high drain bias region. When the drain bias is applied, the grain barrier heights for both sides of the grain boundary become asymmetric and the grain barrier height of the side near the source junction will be lower than that of the side near the drain junction. Fig. 3-11 shows the energy band diagram along the channel under high drain bias. As a consequence, there will be extra carriers injecting from the source junction through the side with lower grain barrier into the channel, resulting in the increased current. This phenomenon is so called the “drain induced grain barrier lowering” (DIGBL) effect [38]. It is more significant for short channel poly-Si TFTs [39], because the electrons drifting from source to drain is easier for short channel.
Impact-ionization effect initiated by DIGBL current is another cause responsible for the kink effect of poly-Si TFTs [40]. When the intrinsic poly-Si TFT operates in the kink regime, the
impact-ionization of carriers occurs in the saturation region in which the lateral electric field is higher than the critical electric field. The impact-ionization mechanism in the saturation region is illustrated in Fig.3-12(a). Fig. 3-12(a) illustrates the multiplication process of the impact-ionization mechanism initiated by the DIGBL current, where ☉ represents the Si atom-site; the arrow with dashed line shows the path of the generated electron-hole pair. The drain-source current includes DIGBL current and impact-ionization current initiated by the electrons. Fig. 3-12(b) illustrates the continuity for the mechanism of the impact-ionization initiated by the DIGBL current. Initially, electrons injecting from the source junction move toward the drain through the transport mechanisms in tandem, by surmounting the grain barriers, diffusing across the depletion regions near the grain boundaries, and drifting through the inversion regions between the depletion regions. This is the transport mechanism described by the interfacial-layer thermionic-diffusion model [41]. The generated electrons and holes, being separated by the high electric field, move toward the drain and source junctions, respectively. When reaching the drain junction, the electron flows originating both from the DIGBL and the impact-ionizations constitute the total drain-source current.
Fig. 3-13 shows the output characteristics of SPC-before-etching and SPC-after-etching samples. The drain current of the devices with SPC-before-etching nano-wire channels are larger than that of the devices with SPC-after-etching nano-wire channels. Figures 3-14(a) and (b) show ID-VD output characteristics of p-channel devices with short channel and long channel, respectively. It is noted that the drain current of the p-channel device is smaller than that of the n-channel device, both biased at the same absolute values of VG, VD, and channel length, owing to the lower hole mobility. According to the results above, we summarize that Samples with split conditions (3), (7), and (8) have better transfer properties, and the characteristics of devices with SPC-before-etching channel are better than those of devices with SPC-after-etching channel. In the next section, we will discuss how to improve the
device characteristics.