Figure 2-4 (a) Cross-sectional TEM picture of the sample(1).
Figure 2-4(b) SEM picture of the sample(1).
Figure 2-5 Cross-sectional picture of sidewall spacer nano-wire channel of sample(2) by TEM.
Figure 2-6 Cross-sectional picture of sidewall spacer nano-wire channel of sample(3) by TEM.
Figure 2-7 Cross-sectional picture of sidewall spacer nano-wire channel of sample(4) by TEM.
Figure 2-8 Cross-sectional picture of sidewall spacer nano-wire channel of sample(6) by TEM.
Figure 2-9 The cross-sectional picture of sidewall spacer nano-wire channel of sample(7) by TEM.
Figure 2-10 Cross-sectional picture of sidewall spacer nano-wire channel of sample(8) by TEM.
Figure 2-11 Cross-sectional picture of sidewall spacer nano-wire channel of sample(9) by TEM.
Figure 2-12 Cross-sectional nanowire width and thickness as a function of over etching time by TEM for samples(2), (3), and (4).
Figure 3-1 Typical transfer characteristics of sample(1) and sample(2).
Figure 3-2 Typical transfer characteristics of devices with over etching of 30s and over etching 40s.
n-channel
n-channel, 100nm gate, 100nm channel layer
Figure 3-3 Typical transfer characteristics of devices with over etching of 20s and over etching 25s.
Figure 3-4 Typical transfer characteristics of devices with nanowire thickness of54 and 30 nm.
n-channel, 100nm gate, 50nm channel layer
n-channel, 100nm gate
54 nm, VD = 0.5 V 54 nm, VD = 3 V 30 nm, VD = 0.5 V 30 nm, VD = 3 V
Figure 3-5 (a) Typical transfer characteristics of devices with channel layer SPC before plasma etching and SPC after plasma etching (OE40s).
Figure 3-5(b) Typical transfer characteristics of devices with channel layer SPC before plasma etching and SPC after plasma etching (OE20s).
L=1µm
L=1µm n-channel, 100nm gate, 100nm channel layer
main etching + OE40s
n-channel, 100nm gate, 50nm channel layer, OE20s
Figure 3-6 Typical transfer characteristics of n-channel and p-channel devices.
L=1µm, W=21×2nm
Figure 3-7 Vth and its deviation as a function of channel length.
Figure 3-8 On-state drain current versus channel length at VG=10V and VD=0.5V.
W=21×2nm
SPC before etching
W=21×2nm
SPC before etching
Figure 3-9 (a) ID-VD output characteristics of a short channel device (L = 1µm).
Figure 3-9 (b) ID-VD output characteristics of a long channel device (L = 5µm).
n-channel, SPC before etching W=21×2nm, L=1µm
n-channel, SPC before etching W=21×2nm, L=5µm
Figure 3-10 (a) ID-VD output characteristics of a short channel device (L =1µm).
Figure 3-10 (b) ID-VD output characteristics of a long channel device (L =5µm).
n-channel, SPC before etching W=34.7×2nm, L=1µm
n-channel, SPC before etching W=34.7×2nm, L=5µm
Figure 3-11 Energy band diagram along the channel at VD=0V and VD=high voltage.
VD=0V VS=0V
VD=high voltage VS=0V
eΦb’＜eΦb
Figure 3-12 (a) Cross-sectional view of the saturation region in the intrinsic n-channel poly-Si TFT.
Figure 3-12 (b) Diagram illustrating the current continuity for the
impact-ionization mechanism initiated by the DIGBL current in the intrinsic n-channel poly-Si TFT.
(Reference: Hsin-Li Chen, Ching-Yuan Wu, “A New I-V Model Considering the Impact-Ionization Effect Initiated by the DIGBL Current for the Intrinsic n-Channel Poly-Si TFT’s ”, IEEE Trans. Electron Devices, vol.46, no.4, pp.722-728, 1999.)
Figure 3-13 The ID-VD output characteristics of devices with SPC before and after etching.
Figure 3-14 (a) ID-VD output characteristics of a short p-channel device (L = 1µm).
Figure 3-14(b) ID-VD output characteristics of a p-channel device (L = 5 µm).
p-channel, SPC before etching W=21×2nm, L=1µm
p-channel, SPC before etching W=21×2nm, L=1µm
Figure 3-15 Subthreshold characteristics of as-fabricated device and devices with N2/H2 gas annealing 0.5hr, and NH3 plasma treatment-1hr.
W=35×2nm, L=1µm
Figure 3-16 Transfer characteristics of as-fabricated device and device with 2-hour NH3 plasma treatment at VD=0.5V and VD=3V.
Figure 3-17 Subthreshold characteristics of as-fabricated device and devices that received 1- and 2-hour NH3 plasma treatment at V =0.5V.
Figure 3-18 ID-VG characteristics of devices with SPC before and after etching and received NH3 plasma treatment 1hour.
n-channel, W=34.7×2nm, L=5µm
Figure 3-19 (a) ID-VD output characteristics of as-fabricated device and device with NH3 plasma treatment for 2 hours.(L = 1µm)
Figure 3-19 (b) ID-VD output characteristics of as-fabricated device and device with NH3 plasma treatment for 2 hours.(L = 5µm)
n-channel, W=21×2nm, L=1µm
n-channel, W=21×2nm, L=5µm
Figure 3-20 Leakage current as a function of overetch time for samples with SPC before and after channel etching.
Figure 3-21 (a) ID-VG characteristics of the as-fabricated device with various VD.
Figure 3-21(b) ID-VG characteristics of the device received 2-hour NH3 plasma treatment with various VD.
n-channel, SPC before etching W=21×2nm, L=1µm
n-channel, SPC before etching W=21×2nm, L=1µm
Figure 3-22 (a) Off-state leakage characteristics characterized at various temperatures.
Figure 3-22 (b) Arrhenius plots of the off-state current of 0.8µm n-channel device at different gate voltages. The slope of each line determines the activation energy (Ea).
n-channel, SPC before etching W=21×2nm, L=0.8µm, VD=0.5V
Figure 3-23 (a) Dependency of activation energy on gate and drain voltages for an as-fabricated device.
Figure 3-23 (b) Dependency of activation energy on gate and drain voltage for a device received 2-hour NH3 plasma treatment.
n-channel, SPC before etching W=21×2nm, L=0.8µm
n-channel, SPC before etching W=21×2nm, L=0.8µm
(a) The case of weak electric field.
(b) The case of medium electric field.
(c) The case of strong electric field.
Figure 3-24 The band diagrams for mechanism 1.
Figure 3-25 The gate-drain overlap region and the definition of gate width.
Source
Drain Gate-Drain overlap
Gate-Drain overlap
Figure 3-26 (a) The off-state current with various gate widths at VD=5V.
Figure 3-26 (b) Off-state current with various gate widths at VG=-5V and VD=5V.
n-channel, SPC before etching W=21×2nm, L=0.8µm
n-channel, SPC before etching W=21×2nm, L=0.8µm
Figure 3-27 Dependency of activation energy on gate and drain voltages for a device received 2 hour NH3 plasma treatment.
n-channel, SPC before etching W=21×2nm, L=0.8µm
(a) Low electric field.
(b) Medium electric field.
(c) High electric field.
Figure 3-28 The band diagrams for mechanism 2.
作者簡介
姓名：林賢達 Hsien-Ta Lin 生日：12/15/1980
出生地：玻利維亞
學歷：國立交通大學電子物理研究所碩士班 國立中興大學物理系
台北市立建國高級中學 論文題目：
一種具有奈米線通道的新穎多晶矽薄膜電晶體製作與特性之研究
Fabrication and Characterization of a Novel Polycrystalline Silicon Thin Film Transistor with Nanowire Channels
指導教授：趙天生 博士