Polycrystalline silicon is rich in grain boundary defects as well as intragrain defects, and the electrical activity of these charge-trapping centers profoundly affects the TFT characteristics. To further improve the device performance, it is important to reduce the defects and trap-states in poly-Si film for the poly-Si NW TFT. This could be achieved by using the MILC or ELC to enlarge the grain size of the poly-Si films.
Another important work is to reduce the off-state current with optimized device layout and structure. Furthermore, we may use other materials like the poly-Ge film to potentially enhance the carrier mobility, and the silicide material for S/D to reduce the parasitic resistance.
With suitable optimization, we believe that the performance of poly-Si NW TFTs can be improved significantly. As long as decent performance is achieved, the new NW device can be readily applied to a variety of novel applications in the future.
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Table 2-1 Etching recipe of the high-density plasma and the corresponding etching selectivity of poly-Si to SiO2.
Table 2-2 NH3 plasma treatment conditions.
Pressure
Split
Table 2-4 Summary of the feature size of nano-wire with 100nm gate by TEM.
Split conditions Thickness Width Gate 200nm
Table 3-1 The summary of characteristic parameters with various channel layer thickness and etching time at VD=0.5V. (SPC before etching)
Split conditions Vth (V) SS (V/dec) Mobility (cm2V-1s-1)
Table 3-2 Comparison of characteristic parameters among as-fabricated FG-annealed, and NH3 plasma-treated n-channel devices, all at VD=0.5V.
Table 3-3 Comparison of n-channel device characteristics among as-fabricated, NH3 plasma treatment 1hr, and 2hrs.
Vth As-fabricated 6.36 0.96 19 1.47×105
Forming Gas
annealing-30ms 5.13 0.80 20 1.92×105 NH3 plasma
treatment-1hr 1.66 0.31 34 3.35×106
Vth
Size of NWs Alignment of
NWs Sensitivity Cost & Process
Top-down
Good control Good control Can be high
Expensive, high
Approach Good control Good control
Can be improved by
Table 4-1 Summary of major features of conventional top-down, and bottom-up approaches, and our approach.
Figure 2-1 (a) Device structure of the proposed poly-Si NW TFT.
Figure 2-1 (b) Top-view layout of the poly-Si NW TFT.
A B
Source
Drain
-Wet oxidation (glass substrate) -LPCVD in-situ doped poly-Si -Define gate
-LPCVD TEOS (gate insulator) -LPCVD a-Si channel layer
-Ion implantation
Figure 2- 1 The key process flow of poly-Si NW TFT.
Ion implantation
Dopant atoms
-Dry etching
-Source and drain were covered with P.R.
-Nano-wire channels were formed.
-The cross-section of the line from A to B in the Fig. 2-1(b)
Figure 2-2 Key process flow of poly-Si NW TFT.
Dry etching
Dopant atoms
Figure 2-3 Definition of the nanowire width and thickness.