The small-signal model of intrinsic Y parameters is shown in Fig. 3.8. The analysis is based on the definition of Y parameters and it can be described as below:
, (3.4)
, (3.5)
, (3.6)
. (3.7)
The intrinsic parameters of small-signal model as a function of their Y parameter, Yi, are shown below:
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of the imaginary part of Y parameters versus frequency multiplied by gm. The cross section of an n-type TFT with the corresponding parasitic parameters of small-signal equivalent circuit is shown in Fig. 3.9.
3-3 Experiment and Simulation Analyses
Theoretically extrinsic elements are bias-independent. When Vds = 0V and Vgs <
Vth, the TFT is in the cut-off state. In the cut-off state, as shown in Fig. 3.10, the real parts of Z parameters for a device with channel thickness of 100 nm (L = 0.22μm, W
= 8μm) operated at Vds/Vgs = 0/0V and Vds/Vgs = 0/-1V are shown as a function of frequency. The results decrease with increasing frequency and approach constant values (i.e., Rd, Rs, and Rg), as predicted by Eqs. (3.1)-(3.3). Given the condition of cut-off state, the values of extrinsic resistances gradually become stable as the frequency increases. We also use this scheme to determine the extrinsic resistances for a device with channel thickness of 50 nm (L = 0.22μm, W = 8μm) at Vds = Vgs = 0V and the results are shown in Fig. 3.11. It is found that the extrinsic parameters are Rg = 120.33Ω, Rd = 129.41Ω, and Rs = 8.182Ω.
After subtracting extrinsic parameters, the intrinsic Y parameters can be calculated. Intrinsic elements are theoretically bias-dependent and frequency-independent. The extraction of the intrinsic capacitances is based on Eqs.
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(3.8)-(3.10). The imaginary part of the experimentally measured Y parameters linearly increases with angular frequency as shown in Fig. 3.12 The imaginary part of Y parameters increases with increasing frequency and the slopes of the curves approach constant values (i.e., Cgs, Cds, and Cgd), as predicted by Eqs. (3.8)-(3.10). The gm and ro as a function of angular frequency are shown in Fig. 3.13. Since the variation of gm
with angular frequency is small, we can determine it as the mean value in low frequency range, e.g., < 10GHz. From Eq. (3-11), the ro is inversely proportional to and usually is very small. Thus, a small variation in will cause a dramatic change in ro. The following item determined from the imaginary part of the experimentally measured Y parameters, , is divided by gm
(or ) and shown in Fig. 3.14 as a function of the angular frequency. From Eq.
(3-12), the slope of the curve is τ, which indicates the mean delay time when gate bias and gm change asynchronously. According to the above procedure we obtain the results of intrinsic parameters of the n-type poly-Si TFT (channel thickness = 500Å , L
= 0.22μm, W = 8μm) including Cgs = 6.668fF, Cgd = 2.479fF, Cds = 2.105fF, gm = 0.489mS, ro = 3663Ω, and τ = 1.314psec. Moreover, ft is 8.074GHz and fmax is 11.69GHz, obtained from the measurement of S parameters as shown in Fig. 3.15.
In order to verify the accuracy of the small-signal model, we use the software
“Advanced Design System (ADS)” (Agilent Technologies) to simulate and compare
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with the experimental results. The frequency range is set to be from 0.2GHz to 40GHz at Vd = 2V and Vg = 4V. We apply the extracted parameters in the small-signal model to simulate and compare the outcome with measured results of S parameters in Fig.
3.16. As can be seen in the figure that the simulation results correspond well with the measured data, confirming that the small-signal model is accurate.
One thing should be noted in the above results is that Rd is obviously larger than Rs. Considering the fact that the device is symmetrical in structure, Rs and Rd should be identical. This weird trend is attributed to the layout of the test structure and the measurement scheme. The layout of the test device is asymmetrical after the de-embedding process as shown in Fig. 2.6. The error arisen during the de-embedding process is also an issue. Additionally, the grain boundary of poly-Si should also affect the resistance.
The above procedure is also applied to a device with channel thickness = 1000Å (L = 0.22μm, W = 8μm) and the results are shown in Figs. 3.17-3.20. Similar trends are observed for this device and the results are Rg = 107.93Ω, Rd = 119.932Ω, and Rs
= 7.879Ω for extrinsic parameters, and Cgs = 7.264fF, Cgd = 2.26fF, Cds = 2.413fF, gm
= 0.705mS, ro = 2207Ω, and τ = 1.189psec for intrinsic parameters. The ft is 11.159GHz and fmax is 15.856GHz from the measurement of S parameters at Vd = 2V and Vg = 2V, as shown in Fig. 3.21. A comparison between simulated and measured S
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parameters is shown in Fig. 3.22.
Table 3.3 summarizes the small-signal parameters of the n-type poly-Si TFTs with various channel thickness and width. Broadening the gate width is expected to improve the ac characteristics. Although gm has been improved, the values of parasitic resistance become smaller but the values of parasitic capacitance increase. The gain in resistance components is balanced but the net effect is beneficial for improving ft and fmax.
Both ft and fmax are bias-dependent. An example for ft is shown in Fig. 3.23. The gm increases with increasing Vd, leading to an improved ft as Vd increases. Moreover, as compared with Vg, Vd is much more influential to ft. As the extrinsic parameters (Rg, Rd, and Rs) are ignored, ft and fmax can be respectively expressed as
, (3.14)
. (3.15)
Although the extrinsic resistances are large and may affect the practical ac performance, the above analysis is confirmed with the simulation results and proved to be reliable. Major small-signal parameters extracted at Vd = 2V and various Vg are shown in Fig. 3.24. The corresponding ft and fmax were also measured and shown in Fig. 3.25. Figure 3.26 modifies Fig. 3.25 by normalizing the data to that measured at
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Vg = 1V and compares the experimental results with the theoretical predictions made by Eqs. (3.14) and (3.15). It is observed that the trends of calculation agree well with the measurements.
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Table 3.1 Summary of basic electrical characteristics of n-type TFTs with various channel thicknesses and widths.
Channel thickness = 500Å Channel thickness = 1000Å L/W = with nominal gate length of 0.22μm.
The order of the gate in the
interdigital structure from left side DP SP Number 1 gate 0.185μm 0.210μm
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