2-1 Device structure and Process Flow
The process scheme is shown in Fig. 2.1. First of all, a wet oxide with thickness
of 1000 nm was formed on a six-inch silicon substrate as the buried oxide. An amorphous silicon (α-Si) layer was then deposited with low pressure chemical vapor
deposition (LPCVD) to serve as the channel layer as shown in Fig. 2.1 (a). The channel thickness was either 50 or 100nm. Solid phase crystallization (SPC) method, which was performed at 600℃ in N2 ambient for 24 hours, was then used to transform the film from α-Si into poly-Si in order to promote the electron mobility. The poly-Si
layer was then defined to form active regions by an I-line lithographic and subsequent anisotropic etching steps, as depicted in Fig. 2.1 (b). LPCVD tetraethylorthosilicate (TEOS) oxide with thickness of 10nm was deposited as the gate oxide. Next, a 100nm in-situ phosphorus doped poly-Si was deposited by LPCVD. Subsequently a 25nm
TEOS oxide was deposited to serve as the hard mask material by LPCVD as shown in Fig. 2.1 (c). Afterwards, the gate was defined by a photolithographic step and etched by reactive ion etching (RIE) as shown in Fig. 2.1 (d). A 20nm TEOS oxide layer and
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a 15nm nitride layer were deposited, and then etched by RIE for forming sidewall spacers as shown in Fig. 2.1 (e). A 15nm-thick nickel layer was deposited and then thermally processed at 450℃ by rapid thermal anneal (RTA) in N2 ambient to form Ni-silicide on source, drain, and gate regions. Afterwards source/drain regions were doped by a self-aligned implant with P31+
ions with energy of 10keV and dose of 5×1015cm-2 as shown in Fig. 2.1 (f). A 500nm-thick PECVD oxide layer was deposited to act as the passivation layer in order to prevent the penetration of humidity and impurity. Finally, a metallization process was performed to form metal pads.
To effectively shrink the gate length, we used over exposure and photoresist-trimming techniques to scale down the dimension of the PR patterns. The difference of patterned PR lines with Lmask of 0.25μm located at different dies distributed on a wafer before and after trimming was inspected with the In-line scanning electron microscope (SEM) and the results are shown in Figs. 2.2 and 2.3, respectively. In this thesis, Lmask is the designed length of the structures on the mask, and Lgate is the practical value measured with an In-line SEM. The results of poly-Si line patterns with trimmed PR with Lmask of 0.25μm measured from five dies at different location of a wafer are shown in Fig. 2.4. The measured Lgate ranges from 0.185 to 0.238μm.
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But the trimming method was found to have feet of clay, and the trimmed PR
would collapse when Lgate is further shortened. In this work we thus focus on devices with channel length equals to or larger than 0.2μm. Cross-sectional transmission
electron microscopy (TEM) image of a n-type TFT is shown in Fig. 2.5. The unexpected voids seen in the picture were formed during the preparation of the TEM sample by focus ion beam.
In order to promote ft, we hope hope that the fabricated devices provide high transconductance. The feasible methods to increase transconductance include the decrease in gate length, increase in gate width, and implementation of self-aligned silicidation procedure to reduce the parasitic resistance. Interdigital gate-finger design shown in Fig. 2.6 is adopted to avoid the current crowding phenomenon in the device.
In this work, in addition to the single patterning (SP) method mentioned above to form the poly-Si gates, an additional split of samples with the poly-Si gates patterned with a double patterning (DP) technique [2.1] was also fabricated and characterized.
However, because of the issues resulted from the overlay capability of the I-line stepper and the dimension control of patterns during the manufacturing of the two reticles used for the DP process, severe fluctuation in the dimensions of the final poly-Si gate patterns in the interdigital gate structures is observed. In-line SEM images of the gate patterns formed with the DP and SP techniques are individually
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shown in Figs. 2.7 (a) and (b). Severe gate pattern fluctuation can be identified in Fig.
2.7 (a), while the situation shown in Fig. 2.7 (b) is much better. The cumulative data of the measured Lgate extracted from the two splits of devices with nominal gate length of 0.22μm are shown in Fig. 2.8. In this picture, the measured data range from 0.21 to 0.238μm for the SP split, while the distribution for the DP split is widened from 0.171 to 0.328μm. The different outcome would draw impacts on the device characteristics that are addressed in the next chapter. In this work the RF characterization focuses on the fabricated devices with SP technique for the sake of superior and more uniform device characteristics.
2-2 Measurement Setup
The electrical characteristics of poly-Si TFTs were characterized by an HP4156 semiconductor parameter analyzer. From the I-V curves measured, the characteristics of poly-Si TFTs, such as subthreshold swing (SS), threshold voltage (Vth), leakage current, on/off current ratio, driving current, etc., can be extracted.
The S parameters of poly-Si TFTs were characterized by an HP8510C network analyzer. The measured S parameters were then used to acquire additional properties such as ft, fmax, Y parameters and Z parameters, etc.
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2-3 De-embedded Process
In order to precisely measure the electrical parameters from devices, two steps for correction procedure must be followed. First step is to calibrate the measurement system. It is made by referring to the ideal condition and real outcome. The calibration techniques, such as short-open-load-through (SOLT), through-reflect-line (TRL), line-reflect-match (LRM), are usually employed to define S parameters on the reference plane at the probe tip and promote the accuracy of the measurements [2.2].
Secondly, we have to consider the parasitic effect of the bonding pads and interconnect, because the coupling effects between the metals are significant at high
frequency. The step used for taking away the parasitic effects is called
“de-embedding”.
In this work, we use the SOLT method to calibrate and a two-step de-embedding procedure to remove the parasitic effects via open test fixture and short test fixture.
The SOLT calibration models include short circuit inductance, open circuit capacitance, matching load, and length of the through line [2.3]. The equivalent circuit diagram shown in Fig. 2.9 includes the parallel parasitic capacitances (Yp,1, Yp,2, Yp,3) and series parasitic impedances (Zp,1, Zp,2, Zp,3) surrounding the transistor.
The open test fixture and the diagram of the equivalent circuit equipped with parallel parasitic capacitances are shown in Figs. 2.10 (a) and (b), respectively. The short test
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fixture and the diagram of the equivalent circuit equipped with serial parasitic impedances and parallel parasitic capacitances are shown in Figs. 2.11 (a) and (b), respectively. Firstly, the matrix of parallel parasitic capacitances and serial parasitic impedances is respectively calculated by a simple mathematics presented in Eqs. 2.1 and 2.2,
Yopen: Y-parameter matrix is measured from the open test fixture.
Yshort: Y-parameter matrix is measured from the open test fixture.
Ytransistor: Y-parameter matrix is measured from the transistor.
YDUT: Y-parameter matrix is measured from the transistor with parasitic effect.
, (2.1)
, (2.2) Then, the actual transistor’s Y-parameter matrix without parasitic effects could be obtained using Eq. 2.3:
, (2.3)
Using this two-step procedure the influence of parasitic effects can be lifted and therefore the accuracy of the measurements is assured [2.4].
15 widths of 8 and 64μm, respectively. The devices were patterned with the SP method
mentioned in last chapter. The former device contains only one gate stripe, while the latter is of interdigital type with eight gate stripes connected together. The on-to-off higher than that shown in Fig. 3.1 (b), indicating the effect of fluctuation of the gate