4-1 Summary and Conclusion
In this thesis, we have successfully fabricated and studied the RF characteristics of n-type poly-Si TFTs. An I-line-based DP process was developed and used in the fabrication of the devices. Resistances of source, drain, and gate were reduced with the aid of Ni silicidation technique and implant-to-silicide scheme. RF characteristics of the fabricated devices were characterized and a small-signal model was developed to extract and analyze major parameters.
The characterized devices are with either single or interdigital gate pattern. For devices with identical nominal gate length and various gate width, Ion and Ioff increase reasonably with increasing gate width. However, the drain currents are not strictly proportional to the gate width, owing to the effect of fluctuation of the gate dimensions. The issue is postulated to be resulted from the poor dimension control of the patterns on the two reticles used for the DP process. Severe fluctuation in the dimensions of the final poly-Si gate patterns in the interdigital gate structures is observed. The anomalously shortened gate lengths tend to increase the off-state
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current owing to the short channel effects.
We’ve also successfully extract small-signal parameters by small-signal model.
The simulation results of S parameters agree well with the measured data, confirming that the small-signal model is accurate. We have also studied the variation of parameters at different condition. As compared with the device with single-gate pattern, the values of parasitic resistance become smaller but the values of parasitic capacitance increase in the interdigital gate structure. In addition, the extrinsic resistances are large and may affect the practical ac performance.
4-2 Future Work
There remain some issues to be addressed in this work. It has been demonstrated that the parasitic components would affect RF characteristics and thus it is essential to reduce these parasitic components. Further optimization of the silicidation process can help. Adoption of low-resistance metallic gate materials or novel gate structures is useful to reduce the gate resistance. Refining the re-crystallization to increase grain size of the poly-Si films represents another useful approach for device performance improvement.
The error arisen during the de-embedding process is an issue when we extract
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parasitic parameters. The layout of the through test-structure is needed for de-embedding procedure. The through test-structure can improve the accuracy of de-embedding procedure. On the other hand, tighter CD control during the manufacturing of the reticles for the DP process can help reduce the fluctuation in the dimensions of the final poly-Si gate patterns in the interdigital gate structures. The DP technique is also feasible for producing asymmetric S/D structure in the fabricated n-type poly-Si TFTs. Extra freedoms offered by the asymmetric scheme in the optimization of device structure should be a viable way for further boosting the RF performance of the devices.
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Figures
(a) (b)
(c) (d)
(e) (f)
Fig. 2.1 Process flow of the poly-Si TFT fabrication.
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Fig. 2.2 In-line SEM image of patterned PR lines with Lmask of 0.25μm located at different dies of a wafer before trimming.
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Fig. 2.3 In-line SEM image of patterned PR lines with Lmask of 0.25μm located at different dies of a wafer after trimming.
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Fig. 2.4 In-line SEM image of patterned poly-Si lines located at different dies of a wafer after stripping off the trimmed PR.
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Fig. 2.5 Cross-sectional TEM image of a n-type TFT device.
Fig. 2.6 The device design with interdigital gate structure.
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(a)
(b)
Fig. 2.7 In-line SEM images of poly-Si gates patterned with (a) DR techniques with severe fluctuation and (b) SP techniques with greatly reduced fluctuation.
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Fig. 2.8 Cumulative plots of measured dimensions of poly-Si gates patterned at different dies of a wafer with SP or DP methods with nominal gate length of 0.23μm.
Fig. 2.9 Equivalent circuit diagram used for the two-step correction including parasitic effect [2.2].
0.1 0.2 0.3 0.4