In this section, the memory performances of two novel poly-crystalline silicon thin film transistor, TiN-Al2O3-Nitride-Vacuum-Silicon (Poly-Si TFT TANVAS) and TiN-HfO2-Nitride-Vacuum-Silicon (Poly-Si TFT THNVAS), with a FinFET structure are discussed. The crucial part of the research subject is to combine a high-k blocking layer with a vacuum tunneling layer for a new charge trapping memory device structure.
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3-4-1. Read Disturbance
In order to measure the correct threshold shift of programming and erasing, it is necessary to make sure the measurement will not be interfered by other external elements. One of the typical interference is that the gate bias is too large during the ID-VG measurement, which will cause additional charges injection across the tunneling oxide. Therefore, we need to find out the suitable bias condition of read measurement. Figure 3-12 shows the transfer characteristics of TANVAS memory device when the program bias is set at VGS= 6 V. The transfer characteristics are almost equal within 10-2 second. It proves that read disturbance could be neglected while the gate bias of ID-VG measurement is smaller than 6 V.
3-4-2. Program/Erase Efficiencies of FinFET TANOS and CP TANOS
For all the memory operations in this chapter, no matter TANOS, TANVAS or THNVAS, they are programmed and erased by Fowler-Nordheim (FN) tunneling mechanism.
Continuing the discussion from chapter 2, the corner effect of TiN-Al2O3-Nitride-Oxide-Silicon (TANOS) memory devices are discussed first. We fabricated the FinFET TANOS device with one corner and the conventional planar (CP) TANOS device with no corner. Figure 3-13 and figure 3-14 show the transfer characteristics of the FinFET TANOS device with various programming/erasing times
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at VGS= 12 V and VGS= -12 V, respectively. Figure 3-15 and figure 3-16 show the transfer characteristics of the CP TANOS device with various programming/erasing times at VGS= 12 V and VGS= -12 V, accordingly. It is obvious that both the programming and erasing efficiency of the FinFET TANOS device are much better than the CP TANOS device. Figure 3-17 and figure 3-18 display the comparisons of threshold voltage shifts between the FinFET TANOS device and the CP TANOS device after programming and erasing operation correspondingly. In the programming characteristics, the FinFET TANOS device exhibits a large Vth shift of 2.18 V in 10 ms at a gate pulse of 12 V, while the Vth shift of CP TANOS device is only 1.27 V. In the erasing characteristics, the FinFET TANOS device exhibits a Vth shift of 3.06 V in 10 ms at a gate pulse of -12 V, and the Vth shift of CP TANOS device is 2.82 V It certifies that TANOS memory devices with more corners will enhance the programming and erasing efficiency, and the corner effects in charge trapping memory devices will enlarge the memory window no matter the usage of blocking layer material.
3-4-3. Program/Erase Efficiencies of FinFET TANVAS and FinFET TANOS
We fabricated a novel FinFET TANVAS (one corner) memory device using vacuum tunneling layer. Figure 3-19 and figure 3-20 present the transfer characteristics of the FinFET TANVAS device with various programming/erasing times at VGS= 12 V and VGS= -12 V, respectively. Figure 3-21 and figure 3-22 present the comparisons of threshold voltage shifts between the FinFET TANVAS device and
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the FinFET TANOS device after programming and erasing operation, accordingly. In the programming characteristics, the FinFET TANVAS device exhibits a large Vth
shift of 3.49 V in 10 ms at a gate pulse of 12 V, while the Vth shift of FinFET TANOS device is only 2.18 V. In the erasing characteristics, the FinFET TANVAS device exhibits a Vth shift of 3.84 V in 10 ms at a gate pulse of -12 V, the Vth shift of FinFET TANOS device is 3.06 V. It is obvious that both the programming and erasing efficiency of the FinFET TANVAS device are much better than the FinFET TANOS device. The improvement on programming and erasing efficiency can be attributed to the utilization of vacuum tunneling layer. Vacuum is a low-k material, and utilizing low-k material as tunneling layer would further increase the voltage drop and electric field in the tunneling layer. In addition, voltage drop and electric field would be decreased in the blocking layer and thereby suppress the electron back tunneling effect. Consequently, the programming and the erasing speed would be increased effectively. These results verify that using vacuum tunneling layer is capable of enhancing the efficiency of programming and erasing.
Figure 3-23 and figure 3-24 show the comparisons of threshold voltage shifts of the FinFET TANVAS device with various programming/erasing biases. Figure 3-25 and figure 3-26 show the comparisons of threshold voltage shifts of the FinFET TANOS device with various programming/erasing biases. It is observed that the FinFET TANVAS device always exhibits better programming and erasing efficiency than the FinFET TANOS device even in different programming/erasing bias conditions.
Figure 3-35 and figure 3-36 show the transfer characteristics of the FinFET TANVAS device with various programming/erasing times at VGS= 9 V and VGS= -9 V, respectively. Figure 3-37 shows the threshold voltage shifts of the FinFET TANVAS device with various programming/erasing times after programming and
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erasing operation. In the programming characteristics, the FinFET TANVAS device exhibits a Vth shift of 2.02 V in 10 ms at a gate pulse of 9 V. In the erasing characteristics, the FinFET TANVAS device exhibits a Vth shift of 2.09 V in 10 ms at a gate pulse of -9 V. Even if the programming and erasing biases are only 9 V, the FinFET TANVAS device is still capable of injecting charges across the tunneling layer and producing a 2-V window of threshold voltage shift in 10 ms. It proves that the FinFET TANVAS device which combines high-k blocking layer with vacuum tunneling layer can work well in low voltage operations, and this kind of low power consumption device is very promising in memory industry.
3-4-4. Program/Erase Efficiencies of FinFET THNVAS and FinFET THNOS
We fabricated a FinFET THNVAS memory device and replaced blocking oxide with HfO2. Figure 3-27 and figure 3-28 show the transfer characteristics of the FinFET THNVAS device with various programming/erasing times at VGS= 12 V and VGS= -12 V, accordingly. Figure 3-29 and figure 3-30 show the transfer characteristics of the FinFET THNOS device with various programming/erasing times at VGS= 12 V and VGS= -12 V, correspondingly. Figure 3-31 and figure 3-32 show the comparisons of threshold voltage shifts between the FinFET THNVAS device and the FinFET THNOS device after programming and erasing operation, respectively. In the programming characteristics, the FinFET THNVAS device exhibits a large Vth shift of 3.27 V in 10 ms at a gate pulse of 12 V, while the Vth shift of FinFET THNOS device is only 2.79 V. In the erasing characteristics, the FinFET THNVAS device
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exhibits a Vth shift of 4.99 V in 10 ms at a gate pulse of -12 V, and the Vth shift of FinFET THNOS device is 4.06 V. It is obvious that both the programming and erasing efficiency of the FinFET THNVAS device is much better than the FinFET THNOS device. The improvement on programming and erasing efficiency can also be attributed to the utilization of vacuum tunneling layer. No matter the high-k blocking layer is Al2O3 or HfO2; the vacuum tunneling layers are capable of enhancing the efficiency of programming and erasing.
Figure 3-33 and figure 3-34 show the comparisons of threshold voltage shifts between the FinFET TANVAS device and the FinFET THNVAS device after programming and erasing operation, accordingly. In the programming characteristics, the FinFET THNVAS device exhibits larger Vth shifts than the FinFET TANVAS device before 1 ms programming time. On the contrary, the FinFET THNVAS device presents smaller memory window than the FinFET TANVAS device after 1 ms programming time. The reason why the FinFET THNVAS device exhibits larger windows before 1 ms is that the dielectric constant (k) of HfO2 is larger than that of Al2O3. Utilizing a higher dielectric constant material as a blocking layer will enormously increase the electric field in the tunneling layer and thereby enhance the probability of carrier injection across the tunneling layer. Therefore, the FinFET THNVAS device has faster programming speed and it exhibits larger windows of Vth shifts before 1 ms programming time. When the dielectric constant of materials becomes higher, the energy band gap will become smaller. Due to the lower conduction band level of HfO2, the nitride storage charges will easily tunnel across the HfO2 layer. Charges inject across tunneling layer from channel and charges inject across blocking layer from nitride layer will reach a dynamic balance in a shorter period. Consequently, the curve of threshold voltage shifts of the FinFET THNVAS device will achieve saturation more rapidly than that of the FinFET TANVAS device
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Therefore, the FinFET THNVAS device exhibits smaller windows of Vth shifts after 1 ms programming time. In the erasing characteristics, the FinFET THNVAS device exhibits a Vth shift of 4.99 V in 10 ms at a gate pulse of -12 V, and the Vth shift of FinFET TANVAS device is 3.84 V. It is obvious that the erasing efficiency of the FinFET THNVAS device is much better than the FinFET TANVAS device.
3-4-5. Endurance Characteristics of TANVAS, TANOS, and THNVAS
For memory devices, there should be a reference voltage to distinguish between programming state and erasing state. Differential sense amplifiers will determine the state by judging the relationship between threshold voltage and reference voltage. In N-channel devices, if the threshold voltage is higher than the reference voltage, differential sense amplifiers will determine it’s a programming state. On the contrary, if the threshold voltage is lower than the reference voltage, differential sense amplifiers will determine it’s an erasing state. For fresh memory devices, the reference voltage can be set as the intermediate value between threshold voltages of programming and erasing states, and it will be much easier for differential sense amplifiers to determine the state.
In the endurance measurement, if the threshold voltage of programming state is lower than reference voltage, or the threshold voltage of erasing state is higher than reference voltage, differential sense amplifiers cannot determine the correct states and memory devices will malfunction. Therefore, memory devices which can work well after much more programming/erasing cycles have better endurance characteristics.
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Figure 3-38 and figure 3-39 show the endurance characteristics of FinFET TANVAS device and FinFET TANOS device, respectively. The memory window is 3.12 V in the fresh FinFET TANVAS device and it keeps a 2.7-V window after 104 P/E cycles. In the FinFET TANOS device, the initial memory window is 2.96 V and it keeps a 2.38-V window after 104P/E cycles. The FinFET TANVAS device has less window loss and maintains the memory window well after 104P/E cycles. There will be a higher chance for the FinFET TANVAS device to endure external stress for a long time.
According to the endurance measurements of FinFET TANVAS device and FinFET TANOS device, the curves of threshold voltages go upward gradually. It is worth to mention that the memory devices will lose function when the threshold voltage of erasing state transcends the reference voltage. There are two reasons to explain why the curves of threshold voltages would go upward gradually. The first reason is the stored charges in deep-level traps of nitride trapping layer are hard to be erased. The second reason is that the charges which are trapped in the tunneling layer and the poly-Si/SiO2 interface by external stress, thus degrading the performances of memory devices. Those trapped charges would make the curves go upward more rapidly, and memory devices would malfunction after cycles. For the FinFET TANVAS device, it still works well after 104 P/E cycles. However, differential sense amplifiers in the FinFET TANOS device cannot determine the state after 8500 P/E cycles. It indicates that FinFET TANVAS devices have better endurance characteristics than FinFET TANOS devices. During P/E cycles, less dangling bonds and trapped charges are generated in the vacuum tunneling layer, so the FinFET TANVAS device can work well for a long time and have better endurance characteristics.
Figure 3-40 shows the endurance characteristics of FinFET THNVAS device.
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The memory window is 4.43 V in the fresh FinFET THNVAS device and it keeps a 3.85-V window after 104P/E cycles. The window loss of the FinFET THNVAS device is just little so that the memory window is maintained very well after 104P/E cycles. In addition, just like the FinFET TANVAS device, the FinFET THNVAS device still works well after 104 P/E cycles. It proves that charge trapping memory devices with vacuum tunneling layer can improve endurance characteristics efficiently.
3-4-6. Retention Characteristics of TANVAS, TANOS, and THNVAS
Figure 3-41 and figure 3-42 show the retention characteristics of FinFET TANVAS device and FinFET TANOS device, accordingly. Figure 3-43 shows the comparison of the retention characteristics between FinFET TANVAS device and FinFET TANOS device. The memory window of the FinFET TANVAS device is 1.44 V after extrapolating to retention time of 10 years. The memory window of the FinFET TANOS device is only 0.86 V after extrapolating to retention time of 10 years. Due to the more traps and defects in oxide tunneling layer, it is much easier for charges to flow across tunneling layer by these traps and defects. Therefore, FinFET TANVAS devices have larger retention windows and better retention characteristics.
Figure 3-44 shows the retention characteristics of FinFET THNVAS device.
Figure 3-45 shows the comparison of the retention characteristics between FinFET TANVAS device and FinFET THNVAS device. The memory window of the FinFET THNVAS device is 1.19 V after extrapolating to retention time of 10 years. Although
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the FinFET THNVAS device has a larger initial window, it has a smaller 10-year retention window than that of FinFET TANVAS device. This is because HfO2
blocking layer has smaller energy band gap. The conduction band level of HfO2 is lower than that of Al2O3. It is much easier for charges to flow across HfO2 blocking layer than to flow across Al2O3 blocking layer. As a result, FinFET THNVAS devices have smaller 10-year retention windows as compared with FinFET TANVAS devices.
3-5. Summary
We have demonstrated Poly-Si TFT TANVAS, TANOS, THNVAS, and THNOS memory devices (The electrical characteristics are shown in Table 3-1). Utilizing high-k materials, such as Al2O3 and HfO2, as blocking layer or using low-k materials, like vacuum, as tunneling layer can increase electric field in the tunneling layer and decrease electric field in the blocking layer. Therefore, program/erase efficiency would be enhanced remarkably. For TANOS and THNOS, SiO2/Si interface and SiO2
tunneling layer are liable to be damaged after some program/erase cycles. Using vacuum as tunneling layer can overcome this obstacle and exhibit better endurance characteristics. Traps in oxide tunneling layer and lower barrier of HfO2 blocking layer would provide leakage paths for charges. As a result, the TANVAS memory devices are able to preserve stored charges for a long time and present great retention characteristics.
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