Structure
3-1. Introduction
Oxide is the most typical material which is applied to tunneling layer and blocking layer of the conventional SONOS memory devices. However, the performance of the conventional SONOS memory devices is considered to be not good enough. In recent years, many researchers put much effort in studying some prominent methods to enhance the performance of SONOS memory devices. One of the prominent methods is to exploit high-k material to replace oxide as blocking layer [37]-[39].
If high-k material is used as blocking layer, voltage drop in the blocking layer would become lower and that in the tunneling layer would become higher. Likewise, electric field would concentrate on tunneling region [40]. The higher electric field would increase the speed of programming and erasing at the same time. In addition, lower electric field in the blocking layer would hinder the flow of carriers either from gate to nitride or from nitride to gate. Back tunneling effect would be reduced [41][42], then SONOS memory devices would exhibit better performance and larger window.
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Higher electric field improves the speed of programming and erasing, but it will result in some charges trapped easily in the tunneling oxide and degrade the quality of tunneling oxide [43]-[44]. Then, the phenomenon of stress induces leakage current (SILC) will become more obvious. In terms of retention, more defects in tunneling oxide make more leakage paths exist, and the stored charges will flow across the tunneling layer very easily even no external force is exerted on the memory device. It will present a bad consequence in retention. For endurance, trapped charges will be accumulated in the tunneling oxide after program/erase cycles, and it will lead to the threshold voltages of programmed and erased states move upward more rapidly. If the threshold voltage shift is too large, the memory devices will break down in a short period. Therefore, higher electric field has the chance to diminish the life time of memory devices, and reveal unfavorable effects in endurance.
In order to ameliorate the reliability characteristics, we propose a novel poly-crystalline silicon thin film transistor TiN-Al2O3-Nitride-Vacuum-Silicon (Poly-Si TFT TANVAS) memory device structure which the tunneling oxide is replaced with vacuum. It is difficult for charges to be trapped in the vacuum tunneling layer, so the leakage current and the defects will be suppressed at the same time. It follows that the TANVAS memory device will exhibit better reliability characteristics of retention and endurance. Furthermore, vacuum is a low-k material, and utilizing low-k material as tunneling layer also has the effect of increasing the voltage drop and electric field in the tunneling layer. It means that vacuum tunneling layer is capable of enhancing the efficiency of programming and erasing.
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3-2. Device Fabrication of Poly-Si TFT TANVAS and THNVAS with a FinFET structure
We fabricated novel poly-crystalline silicon thin film transistor TiN-Al2O3-Nitride-Vacuum-Silicon (Poly-Si TFT TANVAS) and TiN-HfO2-Nitride-Vacuum-Silicon (Poly-Si TFT THNVAS) memory devices with a FinFET structure and the fabrication processes will be listed below.
At first, a 1000-nm-thick wet-oxide was thermally grown on 6-inch silicon wafers. Then, a 50-nm-thick Si3N4 film was deposited on wet-oxide by low pressure chemical vapor deposition (LPCVD) system at 780 °C as an etch-stop layer and a 100-nm-thick tetra-ethyl-ortho-silicate (TEOS) SiO2 film was deposited on etch-stop nitride by LPCVD system at 700 °C to be a sacrificial layer. It was patterned with a lithography step and the TEOS SiO2 film was etched by reactive ion etch (RIE) to form several strips with step height of 100-nm. Subsequently, a 100-nm-thick amorphous silicon film was deposited by LPCVD system at 560 °C. After that, it was patterned with a source/drain-pad mask, the amorphous silicon film was etched by RIE to form amorphous silicon spacers, and the amorphous silicon spacers were connected to the source/drain pads which were formed to be the device active region.
Next, a solid phase crystallization (SPC) at 600 °C in N2 ambient for 24 hours was performed to transform amorphous silicon into poly-crystalline silicon.
FinFET structure was formed after etching the 100-nm-thick TEOS SiO2 strips with 3:50 diluted HF, and the etch-stop layer would stop the 3:50 diluted HF etching the buried oxide. Then, a 4-nm-thick TEOS SiO2 film and a 10-nm-thick Si3N4 film were deposited sequentially by LPCVD to be the tunneling layer and the charge trapping layer, respectively. Afterward, a 10-nm-thick Al2O3 film (or HfO2 film) was
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deposited by metal organic chemical vapor deposition (MOCVD) system at 550 °C to be the blocking layer. Behind the deposition of the ANO stack, a 300-nm-thick TiN film was deposited by FSE - cluster - physical vapor deposition (PVD) to be the metal gate (shown in Fig. 3-1).
Following the gate patterning, the TiN gate, Al2O3 blocking layer and Si3N4 trapping layer were etched by RIE, but the 4-nm-thick TEOS SiO2 film was still remained on the wafer. Then, a phosphorous ion implantation was performed with a dosage of 5×1015 cm-2 and an energy of 40 keV. Afterwards, a 300-nm-thick Si3N4
was deposited and it was etched back by RIE to form Si3N4 spacers. Because the Si3N4 spacers wrapped around the Al2O3 blocking layer, they were capable of preventing Al2O3 blocking layer from being etched by the following wet-etching. The tunneling oxide was side-etched for 500-nm with 1:10 diluted BOE to form a vacuum tunneling layer (shown in Fig. 3-2 ~ Fig. 3-6).
Next, a 400-nm-thick passivation oxide was deposited by SiH4-based PECVD system and then the source/drain activation at 950 °C in N2 ambient for 30 seconds was performed. Afterward, contact holes were patterned and the passivation oxide was etched by 1:10 diluted BOE. A 500-nm-thick Al film was deposited by FSE - cluster - PVD subsequently. Finally, metal electrodes were patterned and then the Al metal film was etched to complete the fabrication.