In this thesis, we have dedicated to explore and investigate some new methods of promoting electrical characteristics for charge trapping memory devices. It has been classified into two topics. First, the corner effect of SONOS memory devices, and second, charge trapping memory devices with high-k blocking layer and vacuum tunneling layer.
In order to discuss corner effect of SONOS memory devices, we have fabricated three kinds of Poly-Si TFT SONOS memory devices with a FinFET structure, an omega gate structure, and a GAA structure. Due to the sharp corner geometry, the local electric field of channel/tunneling oxide interface can be enhanced greatly and thereby improve the program efficiency. Additionally, the electric field in the blocking oxide is deservedly diminished accompanying the suppression of electron back-tunneling. The Poly-Si TFT SONOS memory devices with a FinFET structure, an omega gate structure and a GAA structure exhibit a threshold voltage shift of 1.58V, 2.98 V and 3.52 V for FN programming at VGS = +18V in 10 ms. The SONOS memory device with a GAA structure exhibits the highest program speed and it proves that SONOS memory devices with more corners will enhance program efficiency.
We have proposed Poly-Si TFT TANVAS, TANOS, THNVAS, and THNOS memory devices. Utilizing high-k materials, such as Al2O3 and HfO2, as blocking layer or using low-k materials, like vacuum, as tunneling layer can increase electric
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field in the tunneling layer and decrease electric field in the blocking layer. Therefore, the program/erase speed will be enhanced remarkably. In our experiments, the Poly-Si TFT TANVAS memory device exhibits a threshold voltage shift of 3.49 V and 3.84 V for FN program and erase operations at VGS = +12/-12 V in 10 ms, respectively. It presents higher program/erase efficiency than the TANOS memory device. For the TANOS memory device, since the SiO2 tunneling layer is liable to be damaged after program/erase cycles, the TANOS memory device breaks down after 8500 P/E cycles.
In contrary, the TANVAS memory device still works well after 10000 P/E cycles and exhibits better endurance characteristics. This is because the traps in oxide tunneling layer and lower conduction band offset in HfO2 blocking layer will provide leakage paths for charges. As a result, the memory windows of the TANOS and THNVAS memory devices are only 0.86 V and 1.19 V after extrapolating to retention time of 10 years, accordingly. The TANVAS memory device can avoid these problems and possess larger memory window of 1.44 V. Using Al2O3 as blocking layer can preserve stored charges for a long time and presents great retention characteristics. To sum up, the TANVAS memory device shows great performance and reliability characteristics, and it is very promising for future applications in high density circuits and SOP.
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Table 3-1 The electrical characteristics of the FinFET TANOS, TANVAS, THNOS, and THNVAS memory devices.
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Fig. 1-1 The structure of the conventional floating gate nonvolatile memory device.
The poly-Si floating gate is used as the charge storage element.
Fig. 1-2 The structure of the SONOS nonvolatile memory device. The nitride layer is used as the charge-trapping element.
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Fig. 1-3 Proposed trajectory of an emitted channel electron. An energetic electron is redirected toward the interface by an acoustic phonon scattering.
Fig. 1-4 (a) Direct tunneling is associated with transversal of a trapezoidal barrier.
(b) Fowler-Nordheim Tunneling is associated with transversal of a triangular barrier.
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Fig. 1-5 Illustration of Band to band tunneling. (a) Electron-hole pairs appear in the deep-depletion region layer in the n+ drain. (b) The path of electron-hole pair in energy band diagram.
Fig. 1-6 Band diagram of trapped charges loss path in SONOS: trap-to-band tunneling (T-B), trap-to-trap tunneling (T-T), band-to-trap tunneling (B-T), thermal excitation (TE) and Frenkel-Poole emission (PF).
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Fig. 2-1 The cross-section view step of the strip formation for the FinFET structure.
Fig. 2-2 The cross-section view step of the a-Si spacers formation for the FinFET structure.
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Fig. 2-3 The cross-section view step of the nanowire-channel formation for the FinFET structure.
Fig. 2-4 The cross-section view step of the gate formation for the FinFET structure.
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Fig. 2-5 The cross-section view step of the strip formation for the omega gate structure and the GAA structure.
Fig. 2-6 The cross-section view step of the a-Si spacers formation for the omega gate structure.
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Fig. 2-7 The cross-section view step of the nanowire-channel formation for the omega gate structure.
Fig. 2-8 The cross-section view step of the gate formation for the omega gate structure.
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Fig. 2-9 The cross-section view step of the nanowire-channel formation for the GAA structure.
Fig. 2-10 The cross-section view step of the gate formation for the GAA structure.
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Fig. 2-11 The cross-section TEM image after patterning gate for the omega gate structure.
Fig. 2-12 The magnifying cross-section TEM image after patterning gate for the omega gate structure.
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Fig. 2-13 The distribution of electrical field across the stacked ONO dielectrics for the omega gate structure at VGS = 18 V.
Fig. 2-14 The distribution of electrical field across the stacked ONO dielectrics for the GAA structure at VGS = 18 V.
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Fig. 2-15 The distribution of electrical field across the stacked ONO dielectrics for the first corner in the omega gate structure at VGS = 18 V.
Fig. 2-16 The distribution of electrical field across the stacked ONO dielectrics for the second corner in the omega gate structure at VGS = 18 V.
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Fig. 2-17 The transfer characteristics of the FinFET structure memory device with various programming times at VGS= 18 V.
Fig. 2-18 The transfer characteristics of the omega gate structure memory device with various programming times at VGS= 18 V.
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Fig. 2-19 The transfer characteristics of the GAA structure memory device with various programming times at VGS= 18 V.
Fig. 2-20 The comparison of threshold voltage shifts between the FinFET structure, the omega gate structure, and the GAA structure memory devices after programming operation.
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Fig. 2-21 The comparison of subthreshold swing shifts between the SONOS memory devices with a FinFET structure, an omega gate structure, and a GAA structure.
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Fig. 3-1 The cross-section view step of the gate formation before etching oxide for the TANVAS memory device.
Fig. 3-2 The cross-section view step of the gate formation after etching oxide for the TANVAS memory device.
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Fig.3-3 The cross-section schematic image after patterning gate and ion implantation.
Fig.3-4 The cross-section schematic image after nitride spacers formed.
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Fig. 3-5 The cross-section schematic image after etching tunneling oxide with 1:10 diluted BOE.
Fig. 3-6 The cross-section schematic image after depositing passivation oxide.
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Fig. 3-7 The tiled view SEM image for the TANVAS memory device.
Fig. 3-8 The tiled view SEM image of multiple nanowire channels for the TANVAS memory device.
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Fig. 3-9 The top view SEM image for the TANVAS memory device.
Fig. 3-10 The designed mask patterns for the TANVAS memory device.
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Fig. 3-11 The magnifying tiled-view SEM image for the TANVAS memory device.
Fig. 3-12 The transfer characteristics of TANVAS memory device when the program bias is set as VGS= 6 V.
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Fig. 3-13 The transfer characteristics of the FinFET TANOS device with various programming times at VGS= 12 V.
Fig. 3-14 The transfer characteristics of the FinFET TANOS device with various erasing times at VGS= -12 V.
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Fig. 3-15 The transfer characteristics of the CP TANOS device with various programming times at VGS= 12 V.
Fig. 3-16 The transfer characteristics of the CP TANOS device with various erasing times at VGS= -12 V.
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Fig. 3-17 The comparisons of threshold voltage shifts between the FinFET TANOS device and the CP TANOS device after program operation.
Fig. 3-18 The comparisons of threshold voltage shifts between the FinFET TANOS device and the CP TANOS device after erase operation.
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Fig. 3-19 The transfer characteristics of the FinFET TANVAS device with various programming times at VGS= 12 V.
Fig. 3-20 The transfer characteristics of the FinFET TANVAS device with various erasing times at VGS= -12 V.
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Fig. 3-21 The comparisons of threshold voltage shifts between the FinFET TANVAS device and the FinFET TANOS device after program operation.
Fig. 3-22 The comparisons of threshold voltage shifts between the FinFET TANVAS device and the FinFET TANOS device after erasing operation.
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Fig. 3-23 The comparisons of threshold voltage shifts of the FinFET TANVAS device between various program biases.
Fig. 3-24 The comparisons of threshold voltage shifts of the FinFET TANVAS device between various erase biases.
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Fig. 3-25 The comparisons of threshold voltage shifts of the FinFET TANOS device between various program biases.
Fig. 3-26 The comparisons of threshold voltage shifts of the FinFET TANOS device between various erase biases.
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Fig. 3-27 The transfer characteristics of the FinFET THNVAS device with various programming times at VGS= 12 V.
Fig. 3-28 The transfer characteristics of the FinFET THNVAS device with various erasing times at VGS= -12 V.
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Fig. 3-29 The transfer characteristics of the FinFET THNOS device with various programming times at VGS= 12 V.
Fig. 3-30 The transfer characteristics of the FinFET THNOS device with various erasing times at VGS= -12 V.
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Fig. 3-31 The comparisons of threshold voltage shifts between the FinFET THNVAS device and the FinFET THNOS device after program operation.
Fig. 3-32 The comparisons of threshold voltage shifts between the FinFET THNVAS device and the FinFET THNOS device after erase operation.
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Fig. 3-33 The comparisons of threshold voltage shifts between the FinFET TANVAS device and the FinFET THNVAS device after program operation.
Fig. 3-34 The comparisons of threshold voltage shifts between the FinFET TANVAS device and the FinFET THNVAS device after erase operation.
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Fig. 3-35 The transfer characteristics of the FinFET TANVAS device with various programming times at VGS= 9 V.
Fig. 3-36 The transfer characteristics of the FinFET TANVAS device with various erasing times at VGS= -9 V.
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Fig. 3-37 The threshold voltage shifts of the FinFET TANVAS device with various programming/erasing times after programming and erasing operation.
Fig. 3-38 The endurance characteristics of FinFET TANVAS device.
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Fig. 3-39 The endurance characteristics of FinFET TANOS device.
Fig. 3-40 The endurance characteristics of FinFET THNVAS device.
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Fig. 3-41 The retention characteristics of FinFET TANVAS device.
Fig. 3-42 The retention characteristics of FinFET TANOS device.
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Fig. 3-43 The comparison of the retention characteristics between FinFET TANVAS device and FinFET TANOS device.
Fig. 3-44 The retention characteristics of FinFET THNVAS device.
100 101 102 103 104 105 106 107 108 109
Programed state VG=10V, 1ms
Erased state VG=-12V,1ms ~1.19V
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Fig. 3-45 The comparison of the retention characteristics between FinFET TANVAS device and FinFET THNVAS device.
100 101 102 103 104 105 106 107 108 109
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簡 歷
姓名: 劉晏廷 性別: 男
生日: 民國 75 年 12 月 26 日 籍貫: 台南市
地址: 台南市立德十一路 29 巷 46 號 學歷: 台南市立第一高級中學
(90 年 9 月 ~ 93 年 7 月) 國立交通大學電機資訊學士班 (93 年 9 月 ~ 97 年 7 月) 國立交通大學電子研究所碩士班 (97 年 9 月 ~ 99 年 7 月)
論文題目: 以複晶矽薄膜電晶體製作新穎高速電荷儲存式記憶體之研究
Study on the Novel High Speed Charge Trapping Memory Devices with Poly-Si TFTs