3-5-3 Bias Enhanced Memory Effect

After removing irradiation, the source and drain biases also help sustain the light-induced ΔVth. The recovery behavior of the light-induced ΔVth is depicted in Fig.

3-37. With almost identical initial light-induced ΔVth, the recovery of ΔVth after light removal is plotted as a function of recovery time with different bias conditions. It is known that after light removal, the equilibrium condition in pentacene is rebuilt. For devices recover with VD = VS = VG = 0 V, holes produced by thermal generation or by source and drain injection recombine with trapped electrons in pentacene.

Light-induced ΔVth is eliminated with recovery time as shown by the white circle symbols in Fig. 3-37. For devices recover with VD = VS = -15 V and VG = 0 V, however, the negative drain and source bias impede the injection of holes. The trapped electrons in pentacene are mostly kept and the light-induced ΔVth is sustained.

In our experiment, the light-induced ΔVth is sustained for over 5000 seconds and is

erased by removing the drain and source biases or by applying positive drain and source biases. The measurement of the device transfer characteristics every 500 seconds does not affect the ΔVth signal.

3-6 Conclusions

In this chapter, the usual reliability issues of OTFT in bias stress measurement or under prolonged illumination are discussed. Based on the drain bias influence on Vth

of OTFTs, the shift of Vth of OTFTs with SiO2 dielectric is proportional to the channel charge amount as in a-Si:H TFTs. For threshold voltage shift of OTFT under positive and negative pulsed gate bias stress, influences of pulse width, relaxing duration, and trap response time on threshold voltage shift was investigated. For negative pulsed bias stress, the pulse width effect on device ΔVth can be well explained by using RC equivalent circuit and simulated with an equation (Eq. (3-4)) derived from state creation mechanism. For positive pulsed bias stress, drastically suppressed ΔVth

without pulse width dependence was obtained. Since devices under positive gate bias were operated in off-state, a slow accumulation of electron carriers or a slow response of acceptor-like traps were plausible reasons for the long response time (> 2.5 ms).

Finally, threshold voltage shift affected by light-induced electron concentration was studied. It demonstrated that the threshold voltage shift obviously depends on light-induced electrons. Using drain bias and source bias can effectively adjust the amount of accumulated electrons in channel even when the gate electrode was connected to ground.

Gate

Fig. 3-1 Schematic structure of top-contact pentacene-based thin film transistor.

A 100-nm-thick thermal oxide is used as gate dielectric.

Gate Bias ( V )

Fig. 3-2 The linear-region initial transfer characteristic of OTFT. The gate bias is swept from 10 V to -35 V when drain bias is kept at -6 V. The threshold voltage (Vth) is extracted by using the linear region equation.

Gate Bias ( V )

-35 -30 -25 -20 -15 -10 -5 0 5 10

-Drain Current ( A )

10^-13 10^-12 10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5

Initial

V_G - V_thⁱⁿⁱ = - 5V V_G - V_thⁱⁿⁱ = - 10V V_G - V_thⁱⁿⁱ = - 15V After stress time 2000 sec

Fig. 3-3 The linear-region transfer characteristics of OTFTs before and after 2000-sec gate bias stress. The stress conditions are: VG – Vthini = -5 V, -10 V, and -15 V, VDS = 0 V.

Gate Bias ( V )

Fig. 3-4 (a) The evolution of linear-region transfer characteristics when y-axis is in logarithm scale during a 2000-sec gate bias stress. The stress conditions are:

VG – Vthini = -5 V, -10 V, and -15 V, VDS = 0 V.

Fig. 3-4 (b) The evolution of linear-region transfer characteristics when y-axis is in linear scale during a 2000-sec gate bias stress. The stress conditions are: VG – Vthini = -5 V, -10 V, and -15 V, VDS = 0 V.

Stress Time ( sec )

0 500 1000 1500 2000

Threshold Voltage Shift ( V )

-6

-5

-4

-3

-2

-1

0

V_G - V_thⁱⁿⁱ = -15 V V_G - V_thⁱⁿⁱ = -10 V V_G - V_thⁱⁿⁱ = -5 V

Fig. 3-5 (a) the shift of threshold voltage as a function of stress time when gate stress bias (VG – Vthini) are -5 V, -10 V, and -15 V while VDS is 0 V.

Stress Time ( sec )

0 500 1000 1500 2000

Mobility Shift ( cm2 /Vs )

-0.10 -0.05 0.00 0.05 0.10

V_G - V_thⁱⁿⁱ = -15 V V_G - V_thⁱⁿⁱ = -10 V V_G - V_thⁱⁿⁱ = -5 V

Fig. 3-5 (b) the shift of field-effect mobility as a function of stress time when gate stress bias (VG – Vthini) are -5 V, -10 V, and -15 V while VDS is 0 V.

Stress Time ( sec )

10¹ 10² 10³ 10⁴

-Threshold Voltage Shift ( V )

1 10

V_G - V_thⁱⁿⁱ = -5 V V_G - V_thⁱⁿⁱ = -10 V V_G - V_thⁱⁿⁱ = -15 V

Fig. 3-6 The shift of threshold voltage as a function of stress time in logarithm scale when gate stress bias (VG – Vthini) are -5 V, -10 V, and -15 V while VDS is 0 V.

Stress Time ( sec )

0 500 1000 1500 2000 2500 3000

Threhisl Voltage Shift ( V )

-6

-5

-4

-3

-2

-1

V_G - Vth

ini = -15 V, V_D = 0 V Theoretical curves

Stress Time ( sec )

10¹ 10² 10³ 10⁴

-ln[ 1 - ΔVth/(VG - Vthini ) ]

0.1 1

E_A = 0.57 eV

β = 0.283

Fig. 3-7 The threshold voltage shift as a function of stress time. The simulated curve given by Eq.(1) is plotted with the parameters (β = 0.363, EA = 0.56 eV and τt = 3.61×10⁴ sec ). The dispersion parameter β can be obtained by plotting

[ ]

{

^{ln1 ( / )/( )}

}

log− −ΔV_th,D Q_G0 Q_G V_GS −V_thⁱⁿⁱ as a function of log(t) as shown in the inset. Stress bias condition: gate stress bias (VG – Vthini) is -15 V while drain bias (VDS) is 0 V

Gate Bias ( V ) After stress time 2000 sec

Gate Bias ( V ) After stress time 2000 sec

Gate Bias ( V )

After stress time 2000 sec

Gate Bias ( V )

After stress time 2000 sec

Fig. 3-8 (a) and (b) The linear-region transfer characteristics of OTFT before and after 2000-sec gate bias stress when different drain biases (VDS = 0 V, 5 V, 10 V, and 15 V) are applied to devices while gate bias (VG – Vthini) is fixed at -15 V.

Stress Time ( sec )

0 500 1000 1500 2000

Mobility Shift ( cm2 /Vs )

-0.10 -0.05 0.00 0.05 0.10

V_G - V_thⁱⁿⁱ = -15 V, V_D = 0 V V_G - V_thⁱⁿⁱ = -15 V, V_D = -5 V V_G - V_thⁱⁿⁱ = -15 V, V_D = -10 V V_G - V_thⁱⁿⁱ = -15 V, V_D = -15 V

Fig. 3-9 The shift of mobility as a function of stress time when different drain biases (VDS = 0 V, 5 V, 10 V, and 15 V) were added to the bias-stress measurement while the gate bias was fixed as VG – Vthini = -15 V.

Stress Time ( sec )

0 500 1000 1500 2000

Threshold Voltage Shift ( V )

-6

-5

-4

-3

-2

-1

0

V_G - V_thⁱⁿⁱ = -15 V, V_D = 0 V V_G - V_thⁱⁿⁱ = -15 V, V_D = -5 V V_G - V_thⁱⁿⁱ = -15 V, V_D = -10 V V_G - V_thⁱⁿⁱ = -15 V, V_D = -15 V

Fig. 3-10 The shift of threshold voltage as a function of stress time when different drain biases (VDS = 0 V, 5 V, 10 V, and 15 V) were added to the bias-stress measurement while the gate bias was fixed as VG – Vthini = -15 V.

Stress Time ( sec )

10¹ 10² 10³ 10⁴

Threshold Voltage Shift ( V )

1

Fig. 3-11 The shift of threshold voltage as a function of stress time in logarithm scale when different drain biases (VDS = 0 V, 5 V, 10 V, and 15 V) were added to

Stress Time ( sec )

0 500 1000 1500 2000 2500 3000

Threhisl Voltage Shift ( V )

-6

-5

-4

-3

-2

-1

V_G - V_thⁱⁿⁱ = -15 V, V_D = 0 V V_G - V_thⁱⁿⁱ = -15 V, V_D = -5 V V_G - V_thⁱⁿⁱ = -15 V, V_D = -10 V V_G - V_thⁱⁿⁱ = -15 V, V_D = -15 V Theoretical curves

Stress Time ( sec )

10¹ 10² 10³ 10⁴

-ln[ 1 - ΔVth / (VG - Vthini ) ]

0.1 1

β = 0.283 E_A = 0.57 eV

Fig. 3-13 The restored threshold voltage shift as a function of stress time. The theoretical curve given by _{th D},

(

_G0/ _G

)

( _{G th}ⁱⁿⁱ) 1 exp t

V Q Q V V

β

τ

⎧ ⎡ ⎤⎫

⎪ ⎛ ⎞ ⎪

Δ × = − ⎨⎪⎩ − ⎢⎢⎣−⎜ ⎟⎝ ⎠ ⎥⎥⎦⎬⎪⎭ is

also plotted with the parameters given in Ref. [10]. The dispersion parameter β can be obtained by plotting ^log

{

^{−ln 1⎡}⎣ ^{− ΔVth D, (QG0/QG) /(VGS −Vthini)⎤}⎦

}

as a function of log(t) as shown in the inset.

V_D = -6 V,

Fig. 3-14 The linear-region initial transfer characteristic of OTFT. The gate bias is swept from 10 V to -35 V when drain bias is kept at -6 V. The threshold voltage (Vth) is extracted by using the linear region equation.

Gate Bias (V)

Fig. 3-15 The linear-region transfer characteristics of OTFTs before and after 2000-sec gate bias stress. The stress conditions are: VG – Vthini = -20 V, VDS = 0 V.

Stress Time (sec)

0 500 1000 1500 2000

Mobility ( cm2 /Vs )

Subtreshold Slop ( V/decade )

0.6

0 500 1000 1500 2000

Mobility ( cm2 /Vs )

Subtreshold Slop ( V/decade )

0.6

Fig. 3-16 The shift of mobility and the shift of subthreshold slopes as a function of stress time during gate bias stress. The stress conditions are: VG – Vthini = -20 V, VDS = 0 V.

E_A = 0.56 eV

Stress Time ( sec )

0 500 1000 1500 2000

Threshold Voltage Shift ( V )

-8

Fig. 3-17 The threshold voltage shift as a function of stress time. The simulated curve given by Eq.(1) is also plotted with the parameters (β = 0.363, EA = 0.56 eV). The dispersion parameter β can be obtained by plotting

{

^⎡⎣ ^{Δ th G0 G GS thini ⎤}⎦

}

Fig. 3-18 The cross-section of pentacene-based TFTs; pulsed voltage is applied to the gate electrode and source and drain were grounded.

Time ( s ) Voltage ( V )

V_p

V_b

t_p

t_b Period

Time ( s ) Voltage ( V )

V_p

V_b

t_p

t_b Period

Fig. 3-19 The scheme of pulse bias function.

Effective Stress Time (sec)

0 500 1000 1500 2000

Threshold Voltage Shift ( V )

-8

-6

-4

-2

0

Steady-State Bias Stress 2.5 ms

100 μs 50 μs 10 μs 3 μs

Fig. 3-20 The threshold voltage shift curves under steady-state gate bias stress and negative pulsed gate bias stress are plotted as a function of effective stress time. Pulsed gate bias conditions: the pulse width ranges from 2.5 ms to 3 μs, the duty-cycle is 50% of the pulse period, peak voltage = VG = Vthini - 20 V, VDS = 0 V, and based voltage = 0 V. Steady state bias stress condition: VG = Vthini - 20 V, VDS

= 0 V.

R_S

Q_i C_i

C_S Q_S

Gate

Ground Pulse bias

R_S

Q_i C_i

C_S Q_S

Gate

Ground Pulse bias

Fig. 3-21 The equivalent circuit of pentacene-based TFTs is used to simulate the negative pulsed gate bias stress effect.

τ_RC = 13 μs

Pulse Width (sec)

10^-7 10^-6 10^-5 10^-4 10^-3 10^-2 10^-1

ΔV thAC- / ΔV thDC-

ΔVthDC--0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2

2000-sec 1500-sec 1000-sec Simulation

Fig. 3-22 The ΔVth ratio (ΔVthAC-/ΔVthDC-) as a function of pulse width. Response time τRC can be extracted by fitting the experimental data with the simulated curve calculated from Eq. (3).

V_G = V_thⁱⁿⁱ - 20 V

Effective Stress Time (sec)

0 500 1000 1500 2000

Threshold Voltage Shift ( V )

-8

0 500 1000 1500 2000

Threshold Voltage Shift ( V )

-8

Fig. 3-23 The calculated curves obtained from Eq.(4) and the experimental data.

The parameters of modified model are β = 0.363, EA = 0.56 eV and τRC = 13 μs.

Fig. 3-24 The waveforms of pulsed bias are formed by fixed peak voltage duration (tp = 2.5 ms) and various base voltage duration (tb = 0.625 ms to 17.5 ms).

Fixed Peak Voltage Duration = 2.5 ms, V_G - V_thⁱⁿⁱ = - 15 V

Base Voltage Duration ( ms )

0 2 4 6 8 10 12 14 16 18

Threshold Voltage Shift ( V )

-3.0

-2.5

-2.0

-1.5

-1.0

2000 sec 1500 sec 1000 sec

Fig. 3-25 ΔVth curves with effective stress time as 2000 sec, 1500 sec and 1000 sec are plotted as a function of base voltage duration. The bias stress conditions:

VG – Vthini = -15 V, VD = VS = 0 V.

Stress condition before recovery:

V_G = V_thⁱⁿⁱ - 20 V, Stress Time = 2000-sec

Recovery Time (sec)

0 500 1000 1500

Threshold Voltage Shift ( V )

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

V_G = 0 V V_G = 3 V V_G = 6 V During recovery:

Fig. 3-26 After 2000-sec stress with VG = Vthini - 20 V, the ΔVth plotted as a function of recovery time when VG = 0, 3, 6 V during recovery.

Peak Voltage V_G = V_thⁱⁿⁱ - 20 V,

Pulse Width = 5 ms, Duty Cycle = 50 %

Effective Stress Time (sec)

0 500 1000 1500 2000

Threshold Voltage Shift ( V )

-6

-5

-4

-3

-2

-1

0

Base Voltage V_b = 0 V Base Voltage V_b = 6 V Base Voltage V_b = 8 V Base Voltage V_b = 10 V

Fig. 3-27 ΔVth curves under bipolar pulsed bias stress as a function of effective stress time. The stress conditions: Peak voltage = VG = Vthini - 20 V, VDS = 0 V, Based voltage = 0, 6, 8, and 10 V. The duty cycle is 50 ％ of the pulse period.

Pulse width was fixed at 5 ms.

Effective Stress Time ( sec )

0 500 1000 1500 2000

Threshold Voltage Shift ( V )

0.0 0.5 1.0 1.5 2.0

Steady-State Bias Stress 2.5 ms

100 μs 50 μs 10 μs 3 μs

Fig. 3-28 The threshold voltage shift curves under steady-state gate bias stress and positive pulsed gate bias stress as a function of stress time are shown. The pulsed gate bias stress conditions: the pulse width ranges from 2.5 ms to 3 μs, the duty-cycle is 50% of the pulse period, peak voltage = VG = 6 V, VDS = 0 V, and based voltage = 0 V. Steady-state bias stress condition: VG = 6 V, VDS = 0 V.

Pulse Width ( sec )

10^-6 10^-5 10^-4 10^-3 10^-2

ΔV thAC+ / ΔV thDC+

0.0 0.2 0.4 0.6 0.8 1.0

Fig. 3-29 ΔVth ratio (ΔVth AC+/ΔVth DC+) as a function of pulse width.

Gate

Fig. 3-30 The illumination system and conventional top-contact bottom-gate pentacene-based TFT. A 100-nm thickness of SiO2 is served as gate dielectric.

Gate Bias ( V )

Fig. 3-31 The transfer characteristics of OTFTs before and after a 500-sec illumination with gate bias. The stress conditions are: VG = 0 V and -10 V, VDS = 0 V.

在文檔中 有機薄膜電晶體與非晶矽薄膜電晶體在偏壓與光照下之可靠度分析 (頁 71-92)