Finally, ΔVth for wide channel device on flat substrate and bent substrate are studied. When stress bias is small, ΔVth for wide channel device on flat substrate and bent substrate are compared in Fig. 6-14 and 6-15. Obviously, ΔVth keeps unchanged for bent substrate with a curvature radius as 15 mm or 7.5 mm. When stress bias is large and self-heating effect appears, ΔVth for wide channel device on flat substrate and bent substrate are compared in Fig. 6-15. Interestingly, ΔVth increases significantly on bent substrate. It is known that outward bending causes tensile stress in the a-Si:H film [14]. When film temperature increases due to self-heating effect, tensile stress accompanies with the elevated temperature may further accelerate the generation of defects and enlarge ΔVth.
6-4 Conclusion
In this study, a-Si:H TFTs are successfully fabricated on colorless polyimide substrates at low process temperature as 160 °C. Device reliability after bias-temperature stress are investigated. Unchanged gate leakage current as 10-13 A indicates that the SiNx layer fabricated at 160 ℃ is stable. Using gate bias stress and two–terminal bias stress at different temperature on devices with various channel widths, threshold voltage shift (ΔVth) due to charged-state creation is well defined.
Moreover, self-heating enhanced ΔVth is firstly observed and investigated. Increasing channel width, drain bias, or substrate temperature enhances self-heating effect. The increased temperature facilitates the generation of defect states and therefore enhances ΔVth. Influence of substrate curvature on the self-heating enhanced ΔVth is also firstly demonstrated.
n+a-Si:H
Fig. 6-1 Schematic diagram of the bottom-gate a-Si:H TFT on polyimide substrate.
Gate Leakage Current ( A )
10-15
Gate Leakage Current ( A )
10-15
Fig. 6-2 Transfer characteristics of the bottom-gate a-Si:H TFT fabricated at 160°C on polyimide substrate.
Drain Bias ( V )
0 5 10 15 20 25 30 35 40 45
Normalized Drain Current ( μA )
0
Normalized Drain Current ( μA )
0
Fig. 6-3 Output characteristics of the bottom-gate a-Si:H TFT fabricated at 160°C on polyimide substrate.
Gate Bias ( V )
Gate Leakage Current ( A )
10-15
Gate Leakage Current ( A )
10-15
Fig. 6-4 Transfer characteristics of the bottom-gate a-Si:H TFT before and after applying 500 sec and 15000 sec gate-bias stress transfer characteristics at 25 °C substrate temperature. Gate leakage current keeps as low as 10-13 A.
Gate Bias ( V )
Fig. 6-5 Transfer characteristics of the bottom-gate a-Si:H TFT before and after applying 500 sec and 15000 sec gate-bias stress at 60 °C substrate temperature.
Gate leakage current keeps as low as 10-13 A.
Stress Time ( sec )
0 500 1000 1500
Threshold Voltage Shift ( V )
0
Threshold Voltage Shift ( V )
0
= 25 V. The experimental data can be well explained by Eq. (1).
Stress Bias, VStress ( V )
0 5 10 15 20 25 30 35 40
Threshold Voltage Shift ( V )
0
Fig. 6-7 ΔVth under different stress bias VStress after 1500 sec at 25°C is plotted as a function of VStress. The experimental data can be well explained by Eq. (1).
Stress Bias, VStress ( V )
0 5 10 15 20 25 30 35 40 45
Theshold Voltage Shift ( V )
0
Temperature = 25oC VStress = VG - Vthini = VD , VS = 0 V
Fig. 6-8 ΔVth as a function of stress bias where VStress =VD = VG – Vthini , stress time is 1500 sec and substrate temperature is 25°C
Channel Width ( μm )
0 20 40 60 80
Threshold Voltage Shift ( V )
5.5 6.0 6.5 7.0 7.5
VStress = VG - Vthini = VD= 30 V, VS = 0 V
Temperature = 25oC Channel Length = 8 μm
Fig. 6-9 ΔVth is plotted as a function of different channel widths where VStress =VD
= VG – Vthini , stress time is 1500 sec and substrate temperature is 25°C.
W / L = 80 μm / 8 μm
Stress Bias, VStress ( V )
0 5 10 15 20 25 30 35 40 45
Threshold Voltage Shift ( V )
0
Calculated Eq. ( 2 ) with various temperature
Vstress = VG - Vthini = VD , VS = 0 V
Fig. 6-10 Characteristic temperature (Tch) extraction by fitting the measured ΔVT with those calculated from Eq. (2). Temperature calculated by the modified self-heating effect model (TSHE) for devices with channel width as 80 μm after 1500-sec stress time is also plotted by triangular symbols. Stress bias VStress =VD = VG – Vthini. Channel length is fixed as 8 μm.
VGSand VDSStress (Self-Heating Occurs)
BSE fittint with various temperatures, while EA&β are fixed
Characteristic Temperature (Tch) Extraction
Model Parameter Extraction ( EA&β ), Only VGSStress (No Self-Heating)
Step 1
Step 2
Step 3
Step 4
VGSand VDSStress (Self-Heating Occurs)
BSE fittint with various temperatures, while EA&β are fixed
Characteristic Temperature (Tch) Extraction
Model Parameter Extraction ( EA&β ), Only VGSStress (No Self-Heating)
Step 1
Step 2
Step 3
Step 4
Fig. 6-11 Steps of extracting the channel temperature from the reliability model.
Fig. 6-12 Schematic diagram of the a-Si:H TFT thermal equivalent circuit. TC is the temperature at the drain side of the channel and T0 is the temperature of the contact pads, which is assumed to be the ambient temperature of the substrate.
Stress Bias, VStress ( V )
0 5 10 15 20 25 30 35 40 45
Device Temperature (o C )
20 40 60 80 100 120
Tch, W = 80 μm Tch, W = 10 μm TSHE, W = 80 μm
Fig. 6-13 Extracted Tch as a function of stress bias for devices with channel width as 10 μm and 80 μm, respectively. Temperature calculated by the modified self-heating effect model (TSHE) for devices with channel width as 80 μm after 1500-sec stress time is also plotted by triangular symbols. Stress bias VStress =VD = VG – Vthini. Channel length is fixed as 8 μm.
Radius of curvature
Flat 15 mm 7.5 mm
Threshold Voltage Shift ( V )
4
Fig. 6-14 Comparison of ΔVth for wide channel device on flat substrate and on bended substrate when VStress =VD = VG - Vthini
= 25V or VStress = VG - Vthini
= 25V.
Radius of curvature
Flat 15 mm 7.5 mm
Threshold Voltage Shift ( V )
4
Fig. 6-15 Comparison of ΔVth for wide channel device on flat substrate and on bended substrate when VStress =VD = VG – Vthini
= 35V or VStress = VG - Vthini
= 35V.
Chapter 7
CONCLUSION
In this thesis, the reliability issues of low-temperature organic thin film transistor and low-temperature a-Si:H thin film transistor are investigated.
For organic TFTs:
Pentacene thin film is used as the active layer. We discuss the bias stress issues and the light-induced threshold voltage shift of OTFTs. We also investigate the electric field effect of organic phototransistor. Finally, a new sensitive OPT with memory ability and with a large detectable range is proposed.
Bias Stress Effect:
Under steady-state bias stress condition, we firstly investigate the drain bias effect on bias-stress effect (BSE) in pentacene-based OTFTs with SiO2 dielectric. It is found that the shift of Vth is proportional to the channel charge amount while the channel charge amount is adjusted by drain bias. When using pulse bias to stress OTFTs, the ΔVth of OTFTs under positive and negative pulsed bias stress are studied.
Influence of pulse width, relaxing duration, and trap response time on threshold voltage shift is investigated. For negative pulsed bias stress, the pulse width effect on device ΔVth can be well explained by using RC equivalent circuit and simulated with an equation (Eq. (3-4)) derived from state creation mechanism. The RC delay time as 13 μs may be account for hole transit time or hole trapping time. Additionally, trap release effect on ΔVth during base voltage duration were discussed. When increasing base voltage duration from 3 μs to 17.5 ms with fixed peak voltage duration, ΔVth was unchanged. As a result, Eq. (3-4) is sufficiently accurate without considering trap release effect. For positive pulsed bias stress, drastically suppressed ΔVth without
pulse width dependence was obtained. Since devices under positive gate bias are operated in off-state, a slow accumulation of electron carriers or a slow response of acceptor-like traps were plausible reasons for the long response time (> 2.5 ms).
When devices are stressed by bipolar pulsed bias (with negative bias as peak voltage and positive bias as base voltage), ΔVth was dominated by negative pulsed bias stress.
Different positive base voltages only slightly decrease ΔVth.
In further study, we spin-coat Poly(methyl methacrylate) (PMMA) and poly(4-vinyl phenol) (PVP) thin film to modify the surface of SiO2 gate insulator. For devices with PVP-modified gate insulator, incomplete cross-linking produce hydroxyl (OH) groups on dielectric surface. OH groups cause hysteresis in the transfer characteristic of PVP-OTFT when exposed to the light. Then, under positive gate bias stress, significant negative-charged states appears at pentacene/dielectric interface because OH groups react with moisture to cause electron trapping. When applying positive gate bias to device in vacuum, it is found that light-induced threshold voltage shift is not affected by OH groups. Since light-induced threshold voltage shift (ΔVthLight) is caused by light-induced electron trapping at pentacene/dielectric interface, it is found that electron trapping may have two independent sources. One is from light irradiation, the other is from the reaction between OH groups and moisture.
Photo–Irradiation Effect:
In Ch. 3 and Ch. 5, the light-induce electrons and the photoelectric field effect are discussed. Firstly, it is found that the light-induce electrons can be adjusted by varying the electric field distribution of the device channel. In the further study, it is verified that even when vertical electric field plays a dominant role in enhancing ΔVthLight, the removal of light-induced holes through source/drain electrodes is necessary to allow light-induced electrons to be effectively trapped by interface states
as discussion in Ch. 5. When increasing PL, the maximum ΔVthLight of OPT is restricted owing to the fixed amount of interface trap states under a constant gate bias.
Increasing the positive gate bias extends the response window to larger PL and improves Rph to very weak light. Finally, the repeated OPT response to different PL is confirmed by applying periodic voltage signal cycle. These results are useful to design OPT in image sensor array. To date, the origin of electron trapping states is not clear. We had measured the devices in vacuum to suppress the influence of oxygen and water. Significant photoelectric field effect was still observed. Further studies need to be conducted to explore the mechanism in depth.
For a-Si:H TFTs on the Polyimide Substrate:
In this study, we measure and analyze a-Si:H TFTs fabricated by Industrial Technology Research Institute, Taiwan. Devices are successfully fabricated on colorless polyimide substrates at low process temperature as 160 °C. With process temperature lower than 160°C, mobility, threshold voltage and subthreshold slope of a-Si:H TFTs are 0.42 cm2/Vs , 7 volts and 0.77 V/decade, respectively. These parameters of transfer characteristic of low-temperature process device are comparable for the conventional process device. However, low-temperature process still causes more serious reliability issue. There reliability issues have been discussed in the Ch. 6.
Device reliability after bias-temperature stress is investigated. Unchanged gate leakage current as 10-13 A indicates that the SiNx layer fabricated at 160 ℃ is stable.
Using gate bias stress and two–terminal bias stress at different temperature on devices with various channel widths, threshold voltage shift (ΔVth) due to charged-state creation is well defined. Moreover, self-heating enhanced ΔVth is firstly observed and
investigated. Increasing channel width, drain bias, or substrate temperature enhances self-heating effect. The increased temperature facilitates the generation of defect states and therefore enhances ΔVth. In this study, the thermal the thermal equivalent circuit is used to estimate the variation of the temperature increase induced by self-heating effect when changing glass substrate to polyimide substrate. Additionally, the reliability model is used to calculate the channel temperature. The result verifies that device on the PI substrate has more serious self-heating effect. Influence of substrate curvature on the self-heating enhanced ΔVth is also firstly demonstrated.
Summary
In pentacene-based OTFT experiments, the defect generation process of OTFT is sensitive to ambient light and air. Therefore, the stability of OTFT is needed to over the superior passivation layer. To date, there are many groups to continuously research and develop the suitable material. However, these features can be applied on the sensor field. For light detector application, the pentacene-based phototransistor shows the superior photosensivity. Therefore, the pentacene-based phototransistor has potential to develop low-cost scanner on flexible substrates.
Although the transfer characteristic of a-Si:H TFTs fabricated at 150 oC process temperature is comparable to that fabricated at 350 oC, the reliability of device is degraded by lowering the process temperature. Compare with pentacene-based OTFT, a-Si:H TFTs fabricated at 150 oC process temperature is still more stable in ambient air. In Ch. 6, the self-heating effect is observed in the a-Si:H TFTs and it is also found that the low thermal conductivity of polyimide substrate enhances the self-heating effect. However, the relative self-heating effect is never observed in OTFTs and this part needs more experiments to study.