Nyquist frequency is a fundamental frequency that should be used to sample an analog continuously waveform without loss of information. In wireless applications, a baseband processor usually applies a sampling frequency that is more than Nyquist rate, say 4x or 8x of signal bandwidth, to acquire more accurate signal sampling and better signal quality. This high-rate sampling, however, increases ADC circuit operation power and complicates digital signal processing, resulting in about 1/3 of total chip power of both RF and baseband. In other words, the ADC sampling frequency is highly correlated to the circuit operation power. An effective power reduction approach for the whole system is to reduce the sampling frequency to the symbol rate whereas the system performance is maintained.
Accordingly, this chapter describes a power reduction scheme, dynamic sample-timing control (DSTC), which enables a baseband receiver sampling incoming waveforms at the frequency that is equal to the symbol rate in the transmitter. This symbol-rate sampling behavior minimizes operation efforts in an ADC circuit, resulting in minimized ADC operation power. At the same time, the loading of digital signal processing is reduced. This data converter controlling is regarded as a digitally-based analog circuit controlling in a system level design. This DSTC collaborate signal process techniques from a baseband to smartly control an analog/digital converter (ADC) for reduced ADC sampling frequency. This lowered
sampling frequency dramatically reduces overall power consumption in a wireless baseband circuit operation. The role of this DSTC scheme is introduced as shown in Fig. 4-1.
Digitally-Based Analog Circuit Calibration/Controlling
Digital Design
ADIQMC RF Calibration
DSTC Data Converter Controlling
HDC Clock Source Design
DCGPC Chip Implementation
ESCG External Component Elimination
Main Contributions (OFDM Baseband Processor)
System
OFDM Baseband Processor
MAC/
Fig. 4-1. The role of the dynamic sample-timing control in the power and data proximity scheme
Power consumption in a wireless device can be roughly divided as 1/3 from RF, 1/3 from data converter, and 1/3 from baseband signal process. It is found that
possible ways for power reduction are to reduce the power from each building block or to change the controlling behaviors between those circuits. Accordingly, this proposal is going to reduce the circuit power by a proper baseband control to the ADCs to achieve the low power purpose. A relationship of the power versus operating frequency for ADC circuits is revealed in Fig. 4-2. It is found that the power consumed is roughly twice when the operating frequency is doubled. In other words, a proper design and controlling of the ADC circuits to reduce the operating frequency to half frequency will effectively shrink the ADC power consumption to its half, resulting in dramatically power reduction in the whole system. A power budget is shown in Fig. 4-2 that is defined in a wireless system for portable device, ex:
MB-OFDM UWB system [2]. It is found that a pair of ADC circuits operating at the frequency of the signal bandwidth almost consumes the power more than the power budget. If the operating frequency stays at the conventional Nyquist or more than 4x of bandwidth frequency, it meets difficulty to satisfy the system power budget.
Therefore, this chapter describes a methodology applying synchronization techniques to reduce the required operating frequency that is used to drive the ADC circuits, resulting in power reduction.
0 500 1000 1500 2000 0
100 200 300 400 500 600 700
800 ADC Pow er Distribution
Operating Frequency (MS/s)
Power (mW)
6 bits 8 bits 10 bits
[4-14]
[4-15]
[4-16]
[4-17]
[4-19]
[4-14]
UWB Receiver Pow er Limit UWB Signal
Bandw idth
Nyquist Rate
[4-11]
[4-18]
Fig. 4-2. The power and operating frequency for ADC circuits
Timing synchronization plays an important role in ensuring good signal decoding performance, since it determines the sampling timing and frequency of the analog-to-digital converter (ADC) on incoming signals or packets. Existing design approaches apply multi-rate sampling (at Nyquist rate or higher than 4× symbol rate [44][45][46]) to the incoming waveform with a fixed high-rate clock source that drives an ADC circuit. Those high-rate sampled signals are then calculated by an interpolation algorithm [47] to yield a symbol-rate signal stream for data decoding.
This design methodology to designing power-thirsty portable devices is facing increasing difficulty, because both the ADC circuits and the interpolation circuits are operated at a higher processing rate, resulting in higher power consumption.
To enable power reduction with symbol-rate sampling, both Mueller-Muller detection (MMD) [48] and MMD-based timing recovery methods [49] have been proposed under a pulse amplitude modulation (PAM) scheme for best sampling timing search within a sample period. The literature explores the timing
synchronization issue in OFDM systems based on the best block-boundary search for each FFT transformation window [50][51]. However, those studies [50][51] do not guarantee that the signals in each block are sampled at the best sampling timing.
Accordingly, multi-rate sampling schemes [44][45] have been developed to maintain system performance; hence the high-rate operations significantly increase power dissipation.
To maintain system performance and, in the meantime, to reduce power dissipation, this work presents a dynamic sample-timing control (DSTC) scheme for symbol-rate synchronization in OFDM systems, where the optimal sampling timing within a symbol-period interval can be calculated. Unlike multi-rate sampling methods [44][45][46], this DSTC requires aided circuits in a clock source design to generate a phase-tunable clock waveform that corresponds to the best sampling instance as calculated by the DSTC. A digitally-controlled oscillator (DCO) design concept [52] is applied to the phase-tunable clock generator (PTCG) design to enable this symbol-rate DSTC [12] for low-power wireless applications.