The baseline signal modulation and demodulation are illustrated in Fig. 6-2. In the transmitter side, the signal bit stream from the media access control (MAC) layer is first encoded by the forward error control (FEC) code. The output of FEC encoder is represented as bit stream, too. The mapper block takes every one bit or two bits to modulate them into a BPSK or QPSK symbols, depending on the transmitted data rate.
Then some pilot tones are inserted into this symbol stream so that the receiver side may use the pre-known information for timing or frequency synchronization.
Afterwards, an inverse discrete Fourier transformation (IDFT) function block takes the complete symbol stream for the OFDM modulation. Before the digital-to-analog conversion (DAC), the OFDM symbols are reshaped by a pulse shaping block that may perform upsampling digital filtering for spectrum issues or reduce the peak-to-average power ratio (PAPR) by some pre-distortion signal processing. Then, the data converted analog waveforms are carried out by the RF front-end circuits.
FEC
Encoder Mapper Pilot
Insertion IDFT Pulse
Shaping DAC
MB-OFDM UWB Transmitter Side
(a)
FEC Decoder
Equalizer/
Tracking DFT Freq.
Sync.
MB-OFDM UWB Receiver Side
(b)
Fig. 6-2. Block diagrams in the MB-OFDM WUB transceiver (a) transmitter (b) receiver
On the contrary, the receiver side applies a timing synchronization block after analog-to-digital conversion circuits that receive analog waveforms from the RF front-end circuits. This timing synchronization block detects when a desired packet comes so that the following decoding mechanism may wake up for signal demodulation. Moreover, the timing synchronization may also be in charge of generating the best symbol stream that can be provided for the later signal decoding.
After the timing synchronization, the corrected recognized symbols are further calibrated by a frequency synchronization block. This frequency error may come from
any non-ideal circuit implementation and mismatches between a transmitter and a receiver in either a RF circuit or a baseband circuit that may present in terms of a carrier frequency offset (CFO) or sampling clock offset (SCO) phenomenon. Next, the time-domain calibrated symbols are transformed to the frequency domain by a discrete Fourier transformation (DFT) circuit. The frequency-domain signals are composed of primitive information signal and the channel effects. So, the equalizer is applied to estimate the channel information and compensate the channel response.
Although the equalized signals are good enough for later bit-stream decoding, the SCO effects slowly distorts the incoming signals. Consequently, a tracking mechanism is applied to guarantee the stability of the decoding quality after the equalization. Finally, the FEC decoder outputs the primitive information.
System Specifications
Behavior Simulations (MATLAB)
Bit Truncation
Pattern Generation
Hardware Architecture
Wordlength Determination
Hardware Output
Function Match
Fig. 6-3. Developments and verifications between system behavior and hardware implementation
The signal flow of Fig. 6-2 requires the definition of bit length (word length) of each building block operation so that the hardware may be implemented in the corresponding complexity and performance requirements. The determination of bit length is in accordance with the system performance in which an acceptable SNR loss is allowed for the hardware bit length reduction. The total allowable SNR loss is no
more than 3dB in the whole implementation flow. This 3dB design budget is dispread to every possible building block. An in-depth discussion of the quantization evaluations and measurements can be further directed to for complete simulation result disclosure. The brief verification relationship is shown in Fig. 6-3. Based on this baseline modulation and demodulation processor, the added contributions are placed on this platform for the illustration.
According to the baseline signal flow shown in Fig. 6-2 and the proposed contributions DSTC and ADIC RF calibration, the block diagram for this proposal is illustrated in Fig. 6-4. This shows the proposed half-duplex UWB-based modem. The whole baseband system is driven by the clock generated from an all-digital PLL embedded in the chip, and this all-digital PLL generates 528MHz and 1056MHz clock sources from an external 33MHz crystal. In order to make the radio signal easier satisfying power spectrum mask, the baseband signal go through a digital filter with 2x processing rate, i.e. 1056MHz, and sampled by 5-bit DACs before analog circuits. In receiver side, a clock rate with only 528MHz is applied to 5-bit ADCs to prevent from extra ADC power consumption due to higher sampling frequency. To guarantee the signal integrity of sampled data, this 528MHz clock source of ADCs is selected from an all-digital multi-phase generator (MPG), which generates 8 even-delay clock sources in 1.8939ns (1/528MHz), by the dynamic sample-timing controller (DSTC). Moreover, clock drift due to TX/RX clock frequency inconsistency is corrected in clock drift tracking. Furthermore, sampled signals are calibrated in digital circuits with I/Q mismatch effect due to non-balanced RF circuits.
This mismatch can be detected with gain error < 1dB and phase error < 10 degree.
The other standard compliance parameters of ±25ppm carrier frequency offset (CFO) and sampling clock offset (SCO) can be estimated and compensated. The parallel
architecture is also applied in OFDM modem. A 128-point parallel pipelined (I)FFT and division-free channel equalizer are exploited to achieve high throughput requirement.
FEC OFDM TX/RX
5-bit 1. System Clock : 132MHz
2. Throughput : 1056Mbps 3. 128 FFT/IFFT
4. Frequency Sync.
5. Clock Timing Sync.
6. Channel Equalization 7. Parallel-4 Datapath 8. TX filter
OFDM TX/RX TX Band Selection
2
Fig. 6-4. The block diagrams of the proposed MB-OFDM UWB baseband processor
The parallel-four data-path is globally applied to this baseband processor. Due to the high signal bandwidth, say 528MHz, the fundamental clocking speed is operated at the same 528MHz frequency. This high frequency operation approaches the speed boundary of the logic computation or numeric calculation without pipelining in present technology process. This results in the architecture of parallel-four baseband architecture. Accordingly, the timing synchronizer, frequency synchronizer, (I)DFT, and channel equalizer have to correspond to the designed architecture. The