@0.72V
Fig. 6-30. The virtual VDD profile from sleep phase to active phase
Table 6-6 and Fig. 6-31 provide the area percentage of each building block or module in the CPN side. Since this MT-CDMA has a de-spreader synchronizer operating at 5MHz frequency that are 31 times higher than that of baseband signal demodulation processing operating at 5MHz/31 frequency, resulting in a higher area percentage
occupied in the synchronization part (USYNC module), say about 55%. The DSTC operation is included in the synchronization part. The ADIC IQM calibration occupies an about 7.12% of the total area.
TABLE 6-6.THE AREA OF THE MT-CDMACPN CIRCUIT
Module Area(um2) Percentage (%)
URX 517189 100 USYNC 279662 55
UCFO 38127 7.37
UCHANNEL_EST 57959 11.2
UPHASE_RECOVERY 52285 10.11
UFFT16_DIT 43971 8.5
UEQ 5909 1.14 UIQM 36841 7.12
Area Distribution
55%
7%
11%
10%
9%1%7%
USYNC UCFO
UCHANNEL_EST UPHASE_RECOVERY UFFT16_DIT
UEQ UIQM
Fig. 6-31. The pie chart of the area percentage of a MT-CDMA demodulator in a CPN circuit
Table 6-7 and Fig. 6-32 also reveal the power distribution of the whole CPN chip. It is also found that the synchronization part (USYNC) also occupies the most power
percentage of the total CPN chip, say 83%. The wideband ADIC IQM calibration consumes a small portion, about 1.58%, of total power.
TABLE 6-7.THE POWER OF THE MT-CDMACPN CIRCUIT
Unit = nW Leakage Dynamic Total Percentage (%)
URX 162704 1971789 2134493 100
USYNC 92272 1640411 1732683 83
UCFO 10642 79071 89713 4.2
UCHANNEL_EST 17177 84845 102022 4.78
UPHASE_RECOVERY 15801 46131 61932 2.9
UFFT16_DIT 13245 53504 66749 3.12
UEQ 1620 7565 9185 0.43
UIQM 11178 22587 33765 1.58
Total Power Distribution
83%
4%
5%3%3%0%2% USYNC
UCFO
UCHANNEL_EST UPHASE_RECOVERY UFFT16_DIT
UEQ UIQM
Fig. 6-32. The pie chart of the power percentage of a MT-CDMA demodulator in a CPN circuit
As to the dynamic and leakage power ratio, the statistics are shown in Fig. 6-33 and Fig. 6-34. In the applied 0.13μm circuit process, the static power occupies less than 10% power the total chip power. The leakage versus the dynamic power is shown in Fig. 6-34 in terms of the designed modules.
Dynamic vs. Leakage Power 8%
92%
Dynamic Power
Leakage Power
Fig. 6-33. The pie chart of the power percentage of a MT-CDMA demodulator in a CPN circuit in terms of dynamic power and leakage power
Power Ratio in Each Module
11.9% 16.8% 25.5% 19.8% 17.6% 33%
0 20000 40000 60000 80000 100000 120000
UCFO
UCHANNEL_EST UPHASE_RECOVE
RY UFF
T16_DIT UEQ
UIQM
Dynamic Power Leakage Power
Fig. 6-34. The bar chart of the dynamic and leakage power in each operation module
So, the power reduction is shown in Fig. 6-35 in terms of dynamic and static power. By the voltage island approach, both dynamic and static power consumptions are reduced by 60.89% and 38.53%, respectively. With the power island approach, static power is further reduced by 99.92%. The circuit consumes leakage power in most of the time because this system is operated in a small system duty cycle, say 6.96%. Therefore, this static power reduction plays an important role. So, these power reductions meet the body area network’s low power requirements in the WSN side. In the CPN side, a voltage island is applied to scale the supply voltage from 1.2v to 0.8v,
Original Voltage Island
dynamic power
static power
38.53%
60.89%
99.92%
Power Island
60.39%
Original Voltage Island
Dynamic powerStatic power
57.26%
(a) (b) Fig. 6-35. The power reduction in the (a) WSN and (b) CPN
TABLE 6-8.THE MT-CDMA TRANSCEIVER CHIPSET SUMMARY
Item Features
Technology 0.13μm High-Speed/
Low-Leakage CMOS
Max. Data Rate 143kbps
Max. Signal Bandwidth 5MHz
Die Size 1252μm x 1358.8μm (WSN) 1842μm x 1842μm (CPN) Measure Core Power 21μW @ 0.8V (WSN)
566.4μW @ 0.8V (CPN) ADIC IQM Error Tolerance
Gain Error / Phase Error 2dB / 20∘
PTCG Phase Number 8
The proposed MT-CDMA WBAN baseband transceiver is fabricated in 0.13μm 1P8M CMOS process. Table 6-8 shows the chip summary and Fig. 6-36 shows the chip micro-photo. The MT-CDMA is designed in the proposed uPHI system for 10-WSN/CPN 1-meter reliable coexistence. For enduring monitoring, the WSN consumes 21uW with 60.89% dynamic and 99.92% leakage power reduction (total 90.91% power reduction in a 6.96% duty cycle) by the proposed duty-cycle control with power island approach. Fig. 6-37 illustrates the chip measurement scenario.
SRAM
MT-CDMA Modulator
(Power Island) Ctrl
(a)
ADDLL DSTC
Packet Sync
A-IQMC FFT
EQ Pre-FFT
Freq.
Sync.
Post-Freq. FFT Sync.
(b)
Fig. 6-36. Micro-photo of the WSN and CPN chip set in 90nm standard CMOS technology
Fig. 6-37. Testing environment for the MT-CDMA modem test chips
6-3-3 Dual Mode WiBoC OFDM/MT-CDMA Baseband Processor
The second version of the WBAN baseband processor is named as wireless body on a chip (WiBoC). The proposed WiBoC platform contains a WSN and a CPN that are attached on human body skin and integrated in a portable device, respectively.
The system block diagram and behavior time-line are illustrated in Fig. 6-38. A register-based FIFO is designed in the WSN that is used to accumulate body signals from an internally integrated temperature sensor or an external readout sensor. The memory size and clocking speed are optimized for and aimed at the ECG signal that are regarded as the most complex signals among body information sources. Compared to the baseband processing speed, the WSN takes much longer time accumulating body signals. This results in the WSN-CPN pair staying inactive for most of time and awake in burst for data transmission. The baseband processor provides both
MT-CDMA and OFDM modes for selection, and the transmission behavior is shown in Fig. 6-38(b) [3].
The clock sources in the WSN and CPN are implemented by a phase-frequency tunable clock generator (PFTCG). It is used to adjust the generated clock phase and frequency automatically for better system performance and reduced power consumption. An embedded temperature sensor is integrated together. Each block in both the WSN and CPN is designed for a specific power-voltage domain for low-power management.
FIFO OFDM UL-TX
MT-CDMA TX PFTCG
5 MHz
PFTCG 5 MHz OFDM UL-RX
MT-CDMA RX OFDM DL-TX
Temp.
Sensor
OFDM DL-RX
Wireless Sensor Node (WSN)
Variable power domain partitions
Central Processing Node (CPN) Portable Device
(a) MT-CDMA
Mode OFDM
Mode Time
Sleep Phase Active Phase
Downlink (DL)
Sleep Phase
Sleep Phase Uplink (UL)
(Active Phase) Sleep Phase Sign In
(b)
Fig. 6-38. The dual-mode baseband transceiver with (a) abstract view of functional blocks and (b) behavior time-line
This chipset is designed with power-domain partitions for voltage scaling, multi-supply voltage (MSV), and power gating to achieve extreme low power consumption as illustrated in Fig. 6-39.
Temp. Wireless Sensor Node (WSN)
OFDM DL-RX (PGD)
AOD
OFDM UL-TX (PGD) Phase
From external readout circuit To the front-endFrom the front endTiming
Controller
Environmental temperature Data Converters/ RFs/ Wireless Channel
(a)
- UL: Up-Link - DL: Down-Link
- PGD: Power-Gated Domain
- PMC: Power Management Cell - AOD: Always-On Domain
- TD: Transfer Domain 1.0V AOD-TD Central Processing Node (CPN)
OFDM UL-RX (PGD) Synchronizer OFDM
Demodulator PMC
To the front-end
OFDM DL-TX (PGD) Synchronous Symbol
Generator
Data Converters/ RFs/ Wireless ChannelFrom the front end
(b)
Fig. 6-39. The transceiver with power domain planning (a) wireless sensor node (WSN); (b) central processing node (CPN)
With the voltage scaling and multi-supply voltage techniques, the system is partitioned into 12 power domains with possible different voltage supplies. According
to the required operating speed and the achievable functionality, the supply voltage 0.5V is provided globally to every functional block, except special function blocks and transfer-domain (TD) that are operated at 1.0V to interface with I/O pads.
Furthermore, every power domain is not necessary to be activated together. So, the other inactive domains can be switched into sleep phase for most leakage power saving. This active-sleep behavior is achieved by a power management cell (PMC) that contains a distributed coarse-grain power gating cell (DCG-PGC) [65] and an isolation cell shown in Fig. 6-40. The power manager sends commands to the PMC to turn ON/OFF the power-gated domain (PGD). The timing diagram is shown in Fig.
6-41. When an OFF signal is asserted, the isolation cell first de-activates by pulling high the signal in the AOD side. After that, the DCG-PGC shuts the virtual VDD off.
Therefore, the unknown signal from the power-off domain will not affect the other domain. The PMC behavior is in the reverse way when a domain goes to active state.
On the other hand, if a hardware block always stays active, its power will not be gated and is referred as always-on domain (AOD).
DCG-PGC Isolation
Cell
ON/OFF from Power Manager
AOD PGD
Unknown signal Tie-High or Transparent
VDD Virtual
VDD PMC
Fig. 6-40. The power management cell (PMC)
Isolation Cell
DCG-PCG Active phase
~ ~
~ ~
Sleep Wake
Sleep phase Active phase
Fig. 6-41. The power management control sequence
In addition, the chipset has several clock domains to drive different sequential circuits. For the MT-CDMA block, a clock of 1/31 time of the original frequency is needed. Besides, a low frequency to drive the sensor is necessary. Therefore, an embedded clock generator provides the 5MHz clock source, and a clock manager unit is designed for frequency synthesis. The synthesized frequency outputs 5MHz, 161kHz, and 610Hz clocks to cover all possible requirements.