The preliminary investigation of hysteresis in poly-Si TFTs have been performed in this thesis. For the purpose of further enhancing the device performance, some valuable suggestions for future work are listed as follows:
(1) Reducing the programming time of the proposed device is essential for practical application. Since the external resistance of source and drain in our devices is large, it may lead to additional RC delay in operation. To greatly reduce the resistance, we can employ salicide process to the source/drain.
(2) Our results show the use of NW channel can improve subthreshold swing and on/off ratio, while polycrystalline SixGe1-x films can enlarge the hysteresis window and improve the retention characteristics, we can combine the two features to fabricate the poly-Si/ poly-SixGe1-x / poly-Si NW-TFTs. In the NW channel structure, a thin poly-SixGe1-x serving as the major charge storage medium is sandwiched between two poly-Si layers. We expect the proposed structure to effectively enhance the performance of the memory device.
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Fast
* F: minimum feature size
Table 1-1
* F: minimum feature size
Table 1-1
Features of EMBEDDED MEMORIES
BL
WL WL
BL
Fig. 1-1 Comparison between conventional one transistor/one capacitor (1T/1C) DRAM and capacitor-less one transistor (1T) DRAM.
(a)