Up to now, the hysteresis phenomena have been observed under some circumstances discussed in our previous sections. Four important observations are summarized as follows:
(Ⅰ) The hysteresis phenomenon occurs as the poly-Si thickness is sufficiently thin.
(Sec.3-3)
(Ⅱ) The hysteresis phenomenon occurs if poly-Si TFTs skip the post-metal treatments such as FG annealing and NH3 plasma treatment. (Sec.3-4)
(Ⅲ) The window width of the hysteresis and the subthreshold characteristics of FS and RS depend on both maximum and minimum sweeping gate voltage (Vgmin,Vgmax). (Sec.3-5)
(Ⅳ) Window of the hysteresis shrinks as the measurement temperature increases (Sec.3-6).
We‘ve surveyed the literature but found no papers reported similar phenomenon in
poly-Si TFTs. However, this is reasonable based on the above observations. First most of papers reported previously studied the poly-Si TFTs with channel thickness around or thicker than 100nm [52]. In some papers the channel thickness is indeed around or thinner than 50nm, but the hysteresis phenomenon is still lacking [53, 54]. This is attributed to the process sequence of device fabrication. In order to obtain high-performance poly-Si TFTs, it is necessary to reduce the trap-states of the polysilicon films. As a result almost all previously published works [45-51] employed the plasma treatments to passive the defects in polysilicon films. Hence, it is hard to discover the formation of hysteresis.
In this section, a model is developed to explain our interesting finding in poly-Si TFTs. The electrical properties of poly-Si TFTs are different from the traditional MOSFETs. This is due to the presence of grain boundaries (GBs), which result in large threshold voltage (Vth), lower mobility, and high leakage current. Consider an n-channel poly-Si TFT. Assume that the GBs run perpendicular to the channel and no intentional channel doping is performed. So we limit our discussion to a device with a doping concentration below the critical value of N* (N*=NT/Lg), in which NT is the concentration of traps located at the GBs, and Lg is the grain size. The presence of the active traps at GBs provides deep-level trap sites for both electrons and holes and induces band bending with energy barrier height (EB) for carriers. The energy barrier
height is proportional to the defect density (NT) at GBs and to the inverse of the electron concentration (n) induced in the channel by the gate bias [55]. When the gate voltage is gradually applied, the surface potentialΦ should vary along not only the film depth but also the channel direction. Although the electrostatic distribution is a three-dimensional problem, for the purpose of calculating its transport properties, it is sufficient to treat the problem in one dimension as the channel length and width are much larger than the grain size. The associated Poisson equation has been analyzed and calculated [55, 56]. Levinson et al. [57] proposed a model for carrier transport based on Seto’s [55] theory. In this model, the current is governed by thermionic emission above the GBs’ barrier height, and drain current (Id) and the gate bias (Vg) are related with the following relation:
3 2
area; t is the thickness of the channel layer; Vth is the threshold voltage, and is specified in terms of the effective doping Neff and the surface potential Φs. ND is the concentration of shallow donors, Vg and Vds are the gate voltage and drain voltage, respectively. The equation is valid in the subthreshold regime of the transistor.
According our experimental results, the dissimilar transfer characteristics between FS and RS curves which form the hysteresis window can be attributed to the different trap densities of GBs (NT) in the opposite sweeping direction. The Vth of FS is larger related to RS as observed in Fig.3-1. This implies that the trap densities at GBs under FS (NTFS) are higher than that under RS (NTRS). From equations (2) and (3), we can understand that under the same gate voltage condition, the drain current of FS (IdFS) is smaller than RS (IdRS) due to different NTFS and NTRS.
To turn on an n-channel poly-Si TFT, the traps under the quasi-Fermi level in the depletion layer of the surface channel need to be filled by the electrons. This explains why the Vth of poly-Si TFT is larger than traditional MOSFET. Normally, during the RS process, the trapped electrons at the GBs should be immediately de-trapped from the trap sites so that the transfer curve will follow the FS curve and hystersis does not exist. An example is shown in Fig.3-2 for the device with 100 nm-thick poly-Si channel layer. On the other hand, hysteresis is obviously observed for the devices with channel thickness Tch of 30nm and 50nm. This indicates that trapped electrons in the
FS process may retain in the trap sites during the RS process, resulting in a lowering in the Vth and the formation of hysteresis. According to one of our previous publications [58], the depletion width (Wdep) was estimated to be around 60nm for poly-Si layers formed with a scheme identical to this work (e.g., SPC at 600oC in N2
ambient for 24-hours). Correlating this with results of Figs.3-1 ~3-3, it is clear that Wdep plays a key role for the occurrence of hysteresis. When the channel thickness is smaller than Wdep in the channel, the channel becomes fully depleted as the device is turned on; conversely, when the channel thickness is larger than Wdep in the channel, the channel is partially depleted, and in the channel outside the depletion region the potential is not disturbed by the gate voltage, so this region remains neutral. The energy band diagrams for fully and partially depleted conditions at flat-band and on-state modes under FS, and RS is illustrated as shown as Fig. 3-9 and 3-10.
In the case of partially-depleted case (Tch＞Wdep), under the process of FS, the energy bands near the semiconductor surface are bent downward ( Fig.3-9 (b)). In the neutral region ( x＞Wdep ), there are many empty trap states at the GBs with levels distributed in the energy band gap. Nevertheless, in the depletion region ( x＜Wdep ), most of the trap sites under the Fermi level are filled with the induced electrons.
Subsequently, when the RS operation is executed and the bending of the energy band in the depletion region gradually recovers and shifts back to the flat-band condition.
In the meantime, the trapped electrons tend to de-trap from the trap sites. Three possible de-trapping paths are identified in the figures. The first path (the path 1 denoted in Fig.3-9 (c) and Fig.3-10 (c)) is that the trapped electrons at the GBs are released from the trap site to the conduction band by the thermionic emission. The second path (the path 2 denoted in Fig.3-9 (c)) is that the trap-to-trap conduction via the traps located in the neutral region of GBs, and then the electrons move to the neutral region would recombine with holes therein. Consider the energy barrier for paths 1 and 2, we find that energy needed for path 1 (~ 1/2 Eg for deep levels) is bigger than that for the path 2, thus path 2 is more feasible. The third path (as denoted in Fig.3-10 (d) as path 3) is that the de-trapping of electrons to the intra-grain region.
Similarly, it requires a sufficiently high energy for the electrons trapped in the deep levels to leave. Since the path 2 is feasible and efficient as discussed above, we believed it is the major de-trapping path, and the transfer curve under RS operation can promptly follow the FS curve and eliminate the hysteresis, as observed in the devices with a thick poly-Si channel (e.g., Fig.3-2).
In the case of fully-depleted mode ( Tch＜Wdep), the path 2 is hindered by the buried oxide, however. So the available de-trapping paths are paths 1 and 3, both of which require a sufficient energy (or a period of time to acquire the energy) to occur for electrons trapped in a deep level. Hysteresis phenomenon is thus resulted. This
well explains why the hysteresis we observed in the devices with Tch=30nm (Fig.3-3) and Tch=50nm (Fig.3-1).
We can examine the above model by extracting the trap density. If the model is correct, portion of the traps (i.e., those deep states trapped with electrons) become inactive during the RS process. Assume the amount of charges in those inactive traps is QT (Coul/per unit area), the effective trap density in RS case, NTRS, is smaller than that in FS mode, NTFS , with the following relation:
For poly-Si TFT, the subthreshold swing (SS) is affected by the effective trap density, NT, with the following equation [59] :
ln10 1
where CS is the capacitance of interface states at the channel/oxide interface, which is usually negligible in poly-Si TFT. For the results shown in Fig.3-1, the SS are around 460mV/dec and 370mV/dec for the FS and RS I-V curves, respectively. Such difference becomes reasonable with the inference of (5) to (6): SS is reduced owing to the existence of inactive trap states. According Eq.6, an inactive trap density, (equal to
NT
Δ
QT
q ), is extracted to be1.61 10 /x 12 cm2.
according to the following relation:
With this relation, we can approximately estimate the amount of the trapped charges exist during the RS measurement. We used two ways to define the Vth, one is the constant-current method described in Sec.3-2; the other is the intercept of gate voltage of the linear drain current-Vg plots. For the results shown in Fig.3-1, the threshold voltage defined by constant-current method ( th g@ d W 10
V V I 0nA
The extracted threshold voltage is =1.83V for FS mode and =0.29V for RS mode, and is calculated to be around
F
Vth VthR
NT
Δ 1.66 10 /x 12 cm2. The results based on the
threshold voltage difference are very well consistent with that obtained with SS difference1.61 10 /x 12 cm2. These estimated values are also close to that reported in the literature [55-57].
In Sec.3-4, we have discovered that the post-metal treatments have strong influence on the hysteresis. When the devices received post-metal treatments such as FG annealing and NH3-plasma treatment, the deep-level trap density NT is expected to be reduced due to the defect passivation mechanism. The hysteresis window is thus largely shrunk, as shown in Figs.3-4 and 3-5.
In Sec.3-5 section, we found that variation in the gate sweeping range ( ) may have effects on the transfer characteristics of FS and RS, as well as the hysteresis window. By means of our model, we can further realize the effects of and . According our measurement sequence, the sweeping follows the A-B-A sequence as shown in Fig.3-1. FS (A to B) “programs” the device by filling the deep-level traps with electrons and the amount of the stored charges is determined by the . From this argument, it becomes reasonable to understand the results illustrated in Figures 3-6 (a) and (b). The increase in hysteresis width with increasing
is attributed to the increase in the number of electrons trapped in deep levels, since a higher may result in a higher band bending and the amount of deep levels under the Fermi level in the channel would increase accordingly.
min and max
On the other hand, to erase the programmed device, the gate voltage applied in the RS event must be sufficiently low to render an upward band-bending in the channel, so that the stored electrons can be effectively expelled out from the stored sites. Thus the extent of erasing is determined by . In Fig.3-7, transfer curves of a device with fixed but various are measured. We can see that the RS curves coincide due to the fixed . However, the used in the second sweeping (-3V) is not sufficiently low to complete wipe off the stored charges in the channel, so the third sweeping starting at -1V shows a smaller threshold voltage in the
min
FS curve as compared with the former two sweeping.
Figure 3-12 shows the transfer characteristics of devices under consecutive 20 times of measurements following the A-B-A cycles. In Fig.3-12 (a) and are 8V and -3V, respectively. It can be seen that there exists a positive shift in the transfer curves with increasing cycle (indicated by the arrow). This is attributed to the degradation caused by the high . This issue could be solved by reducing the
. An example is shown in Fig.3-12 (b), the shift is transfer becomes negligible as the is reduced to 6V.
max
Vg Vgmin
max
Vg
max
Vg
max
Vg