The fabrication of the NW devices is described in Chapter 2. The cross-sectional
transmission electron microscopic (TEM) image of a device with inverse-T gate is shown in Fig.4-8. In the figure, it can be clearly seen that the location of the NW channels is precisely on the upper-step corners of the inverse-T gate. The perimeter of the triangular NW channel can be characterized in the enlarged view of the NW shown in Fig. 4-8 (b). Lengths of the three edges are 20nm, 30nm and 40nm, respectively. Fig.4-9 compares the transfer characteristics of NWTFTs with those of a conventional planar self-aligned device. Note that the drain current has been normalized to the channel width. The results indicate that the shrinkage of channel dimensions could help improve device performance in terms of higher on-current and steeper subthreshold swing and better control of short-channel effect, which can be ascribed to the increase in surface-to-volume ratio. The inverse-T double-gated (ITDG) -NWTFT can be operated in several operation modes, including single-gated (SG) modes and double-gated (DG) modes. SG modes can be further divided into two types:
MSG and SSG. MSG is to apply the sweeping gate bias to the inverse-T gate electrode while the top-gate is grounded, and vice versa for the SSG mode. In DG mode, both the inverse-T gate and top-gate electrodes are connected together and applied with the sweeping gate bias. The transfer characteristics of ITDG-NWTFT operated in these modes are shown in Fig. 4-10. In the figure, it can be clearly seen that the DG mode shows better electrical characteristics, including steeper subthreshold swing as low as 165 mV/dec. (@Vd=0.1V) and higher on-state current, as compared with SG modes. This could be ascribed to its better gate controllability and larger conducting width. The subthreshold swing for MSG and SSG modes are 253 mV/dec and 313 mV/dec, respectively. This indicates that the inverse-T gate has a better gate controllability. Plasma damage induced during the formation process on the outer surface of the NW next to the top-gate is presumably another factor responsible for the worse subthreshold swing of the SSG mode.
To investigate the hysteresis characteristics of the ITDG-NWTFTs, we apply the gate voltage respectively to the different gate electrodes, i.e., top gate and inverse-T gate. Figure 4-11 shows the results of an ITDG-NWTFT under SSG and MSG modes of operation. It can be seen that he hysteresis phenomena are observed. Because the channel thickness of ITDG-NW is sufficiently thin, the NW channel is fully depleted, and it conforms to the condition that the hysteresis form according our model. The
width of hysteresis for MSG mode is smaller than that for SSG mode. This is ascribed to a higher density of defects on the outer surface of NW channels as we mentioned in the last paragraph.
Figure 4-12 shows the results for the width of hysteresis (H) of the planar and ITDG-NW structure as a function of channel length (L). The sweeping voltage ranges from -3 to 6V in the measurements. As can be seen in the figure, the ITDG-NW structure depicts similar behavior trend as the planar structure, i.e., the channel length exhibits only very minor influence on H. In addition, the H is larger in planar structure than ITDG-NW structure. Owing to the thinner channel thickness in ITDG-NW, the effective trap density (per unit area) in the channel is smaller than that in planar structure, therefore the hysteresis window is also smaller.
We also vary the gate sweeping range to study its effect on the hysteresis window.
Figure 4-13 shows the results of a device operated under MSG mode. In Figs. 4-13(a) and (b) the gate voltage starts at -3V but the highest voltage is varied from 3 to 9V.
Basically the outcome is similar to that of planar structure presented in last chapter. It appears that, with increasing gate voltage, the transfer characteristics of RS mode shifts toward more negative direction and results in an increase of the hysteresis window, as observed in Fig.4-13 (a). The window becomes saturated as the maximum gate voltage reaches a specific voltage (about 8V in the case), as observed in Fig. 4-13
(b). In addition, in Fig. 4-13 (c), the maximum gate voltage is fixed at 6V, while the minimum gate voltage is set at -3 or 1 V, respectively. It is seen that the transfer characteristics of FS mode shifts as the starting voltage is changed, while the curves of the RS mode coincides.
Because of the small volume and thin body of silicon NW, the channel potential is sensitive to both gates, and thus strong gate-to-gate coupling can be observed and would have the capability of tuning the threshold voltage by adjusting the other gate voltage [72]. Figure 4-14 displays the hysteresis characteristics of ITDG-NWTFTs by sweeping the top-gate while biasing the inverse-T gate at a constant value, Vint=-1, 0, or 1V. It is clearly seen that the threshold voltage can be successfully modulated by the inverse-T gate bias. This technique of adjusting the threshold voltage by controlling the bias of the second gate could be applied for low standby power circuits [72]. For the results shown in Fig. 4-14, not only the threshold voltage shifts with Vint, but also the hysteresis window does. With such feature, it is feasible to enlarge the hysteresis window by applying different Vint in FS and RS modes.
Chapter 5
Conclusions and Future Works
5-1 Conclusions
In this study, we report an interesting hysteresis phenomenon in poly-Si TFTs. To observe such phenomenon, the poly-Si channel must be thinner than a characteristic depletion width and receive no passivation treatment. We present a model to explain the finding, based on the electron trapping and de-trapping events occurring in the grain boundaries of the poly-Si channel. The mechanism is new and distinctly different from the origins of hyesteresis phenomena reported in the literature. The proposed mechanism can be verified very well by our measurement results. The effects of several factors such as channel materials, channel length, channel width, temperature, and multiple-gate configuration are also investigated.
Since the hysteresis window exhibiting in the transfer current-voltage characteristics is significant, we also exploit its feasibility for memory device applications. We found that the retention property is better than that of 1-T DRAM, although a long programming time (> 1 ms) is needed.