In 5.2, LLRs of turbo decoder output is used to determine if a CB is corretly decoded.
With this useful information, in the sction, a novel iterative IC is presented. In the proposed scheme, process propagates to the next outer iteration or not depending on the correctness of the CB in current outer iteration. Bits of the correct decoded CBs are hard-decisioned, re-encoded to form the coded bits including systematic bits, parity bits, and tail bits. Then these bits are respread and removed from the received signal. MAI from these correct blocks is thus removed correctly, and we can expect better BER than those with estimated parity bits and tail bits. In addition, large amount of computational complexity and processing time can be saved.
5.3.1 The Generalized Iterative IC
The block diagram of the generalized iterative IC is shown in Fig. 5-8. The basic building blocks of an iterative IC are a soft-in soft-out (SISO) MUD and a bank of K user SISO channel decoder. The function of these blocks is to compute the posterior probabilities based on the given prior probabilities and on the given signal. For the SISO MUD [57], it has two sets of inputs: the MF output, and the a priori information obtained from channel decoder. In the first outer iteration, no a priori information is actually available at the receiver on the transmitted bits. From the 2nd outer iteration, the set of is fed back from the channel decoders. We refer to the set of the feedback LLR as the current bit statistics.
The SISO-US outputs another set of LLR and then deinterleaved according to permutation and sent as input to the SISO channel decoder, which performs the same algorithm, i.e. BCJR, as in turbo decoding. Details on the algorithm can be found in 5.2.1. The output of the SISO channel decoder in current outer iteration, after interleaving, becomes the set of current bit statistics for user in the next outer iteration. In the last iteration, each SISO decoder must also
supply the final estimate of the corresponding information bit stream, which represents the output of the whole receiver.
5.3.2 The Proposed Iterative IC
The structure of our proposed iterative IC is shown in Fig. 5-3. The block diagram of the first outer iteration is shown in Fig. 5-5. Parts of these blocks are introduced in 5.2 as shown in Fig. 5-4 which perform SIC and turbo decoding with stopping criterion, and new blocks added in Fig. 5-5 are used for the next outer iterative processing. At the turbo decoder output, all blocks are separated into two parts. The first part is composed of the detected correct blocks and the other part is composed of the remaining blocks. LLRs of the first part are passing through the block of hard decision followed by the turbo encoder to reconstruct the parity bits and tail bits. All bits are mapped, interleaved and respread, and then removed from the received signal, and the remaining signals are sent as one of the inputs to the second iteration. For the bits in the first part, no further processing is needed.
Only the LLRs of the CBs in the second part are interleaved as one input to the second outer iteration. To re-built the parity bits upx[n] of the incorrect CB, we should utilize the LLR of parity bits where
⎟⎟
⎟
⎠
⎞
⎜⎜
⎜
⎝
⎛
′ ⋅
′ ⋅
′ ⋅
′ ⋅
=
∑
∑
−
−
0 1
) ( ) , ( ) (
) ( ) , ( ) ( log
]) [ (
1 1
S
n n
n S
n n
n px
s s
s s
s s s s
n u
L α γ β
β γ
α
The block diagram of the second to the Io,k-th outer iteration is shown in Fig. 5-6. From the second outer iteration, input to refined channel estimation is the output of TCSR in which all estimated respread user data are cancelled. The SISO user data separator can be MUD such as PPIC, MMSE and etc. with the remaining signal form the first outer iteration and LLRs as input. Here the SISO PPIC [4] with two stages is used. The Decision block
performs soft-decision and the estimated bits at initial stage are as follows. Outputs of the PPIC are de-interleaved, then the LLR as computed for RAKE in [45] are inputs to turbo decoder. Again, variance estimation is done with the aid of pilot-channel signal. The stopping criterion is the same as that in the first outer iteration with the same ordering information. When the decoding (inner) iteration reaches the predefined limit, the process continues to the next outer iteration. To decide if the next outer iteration should be done, a simple method is to discriminate if the bits of a newly-detected correct decoding block are overlapped with the bits in an incorrect CB of other users. The concept of dividing correct and incorrect decoded CBs into two parts has been proposed [8], [41], [46].
In [46], bits in correct CBs are given a high LLR value for equalization in MIMO systems.
However, soft information of bits other than information bits in a correct CB not necessary has the same sign as the original ones. The same problem arises in [8] where only the information bits in a CRC-checked correct CB are soft decision with +1/-1, reconstruct and removed from the correlated signal in orthogonal frequency-division multiple-access code-division multiplexing (OFDMA-CDM) systems. Our proposed method can be viewed as the solution to generate the “genie” re-encoded bits depicted in [41].
5.3.3 Simulation Results and Discussions
In this section, we compare the performance of our proposed iterative IC and the generalized iterative IC which performs turbo decoding with 10 inner iterations, and no correct CB is removed from the received signal. From the 2nd outer iteration, both iterative IC adopt two-stage SISO PPIC with partial coefficient 0.6. The simulation parameters are the same as those in 5.2.3. It is shown is Fig. 5-9 that our proposed iterative IC outperforms the generalized one with 0.5 dB gain at BER=10e-4.
In Table 5-2, the average inner iteration number for turbo decoding used in our proposed method and the generalized method are listed at SNR=5.9 dB. It is shown that large amount of iteration number can be saved.
5.4 Summary
In this chapter, we propose a novel iterative IC with high performance. The SIC front-end at the first outer iteration provides lower BER than PPIC with three stages, and thus better performance can be expected after turbo decoding. A highly efficient and low-complexity stopping criterion utilized the ordering information of SIC is used to find the correct CB and decide if the decoding process can be terminated. Only the bits in incorrect CBs should proceed to the next outer iteration. As a result, huge amount of computational complexity can be saved. When the outer iteration number increases, the improvement in correct decoding becomes smaller. A simple method is proposed to decide if the next outer iteration should be done. Except the timing information, all parameters used in the proposed scheme are estimated from the received signal. Our proposed iterative IC is shown to have smaller computational complexity than the generalized iterative IC with much BER improvement.
Table 5-1 Average redundant iteration number of deciding correct CB versus average false alarm probability at SNR = 6.9dB, 8 users
Average redundant iteration number Average false alarm probability
Genie 0 0
θ=3 5.6e-2 2.2e-3
Checking
full block θ=4 7.1e-2 0
θ=3 5.5e-2 3.0e-3
Proposed
(x= 4) θ=4 7.0e-2 0
θ=3 5.3e-2 3.0e-3
Min-LLR
Proposed
(x= 6) θ=4 6.6e-2 0
Checking full block
θ=0 6.2e-2 1.6e-2
Proposed (x= 2)
θ=0 6.1e-2 1.6e-2
Proposed (x= 4)
θ=0 5.7e-2 1.7e-2
HDA2
Proposed (x= 6)
θ=0 4.5e-2 2.2e-2
Checking full block
θ=1 6.8e-2 0
Proposed (x= 4)
θ=1 6.2e-2 0
θ=1 5.7e-2 7.4e-4
Min-LLR
&&
HDA2
Proposed
(x= 6) θ=3 6.9e-2 0
Table 5-2 Average inner iteration in the proposed method and the generalized iterative method
1st outer iteration 2nd outer iteration 3rd outer iteration Proposed Iterative Method 1.72 2.58 3.30
Generalized Iterative Method 10 20 30
) 1 n(
yp
) 2 n(
yp ) s(n
y
Fig. 5-1 Block diagram of turbo decoder for one user
4.5 5 5.5 6 6.5 7 7.5 8 8.5 9
10-5 10-4 10-3 10-2 10-1
SNR (dB)
BER
Asynchronous Reception,Fading Channel Case 3 with Channel Estimation W=128 bits, 8 Users
PPIC front-end SIC II front-end
Fig. 5-2 BER comparison of turbo-coded systems with SIC II and PPIC at front-end
1st Outer ...
Iteration
2nd~Ioth
Outer Iterations
...
( ) r t
] ˆ1[n u
] ˆ n[ uk
Outer iteration
Fig. 5-3 A novel iterative IC scheme
ˆ( ) r t
Fig. 5-4 Block diagram of SIC at front-end
Fig. 5-5 Block diagram of the first outer iteration of the proposed iterative IC
Fig. 5-6 Block diagram of the 2nd to the Io-th outer iteration
DCSR IC for
pilot VC ( )
r t
Fig. 5-7 Block diagram of variance estimation
SISO User Separator
(MUD) SISO
Decoder SISO Decoder
...
...
...
LLR1[.]
LLR1'[.]
LLRK'[.]
LLRK[.]
Fig. 5-8 Generalized iterative IC
4.5 5 5.5 6 6.5 7 7.5 8 8.5 9
10-6 10-5 10-4 10-3 10-2 10-1
SNR (dB)
BER
Asynchronous Reception,Fading Channel Case 3 with Channel Estimation W=128 bits, 8 Users
1st outer iteration Generalized-2nd outer iteration Proposed-2nd outer iteration Generalized-3rd outer iteration Proposed-3rd outer iteration
Fig. 5-9 BER comparison of our proposed iterative IC and the generalized IC without detection of correct CB
Chapter 6
Conclusions
In this thesis, we analyze the characteristics of SIC and propose techniques and architectures in the hope of making the SIC a practical technique for uplink WCDMA systems in the view of error performance and simplicity.
In Chapter 3, three ordering methods for SIC in the uplink of WCDMA systems over multipath fading channels are discussed and compared in the aspect of the implementation issues (such as reordering frequency, processing delay, latency, and computational complexity), and error performance related parameters (such as pilot-to-traffic amplitude ratio, cancellation-ordering method, grouping interval, received power distribution ratio and channel estimation as well as timing estimation errors). The scheme decides the cancellation order and performs data detection in a group manner for each user. SIC I decides the cancellation order according to average power as that in [90]. In SIC II, the G-bit summation of the RAKE output strengths in each stage are used to find the next detected user. SIC III decides the cancellation order based on the G-bit summation of the RAKE bank output strengths at the first stage.
Channel estimation performed independently with the pilot channel of each user is taken into consideration in the analyses. The interference between traffic channel signals and pilot channel signals are taken into consideration. In order to alleviate these interferences pilot-channel signal of all users are estimated and removed before data detection.
Architectures for the three SICs are presented. To minimize the complexity of the receiver, we adopt the MRC RAKE receiver with hard decision for data detection and
windowed moving average technique for channel estimation.
In addition to consider the single-rate systems, a generalized pilot-channel aided SIC scheme is presented for application in multirate communications. The SIC III is slightly modified to adapt to multirate systems. The characteristics of grouping interval shown in the single-rate systems can be also found in multirate systems.
In Chapter 4, a pilot-channel aided pipeline scheme for SIC is proposed. Generally speaking, pipelined implementation is inherent in SIC but not in channel estimation. This scheme combines channel estimation and user data detection into sequential type with low complexity and leads to pipeline implementation. Compared with conventional channel estimation using correlator output and SIC without pilot signal remover, the proposed scheme shows better quality both on channel estimation and user data detection.
We propose a pilot channel aided adaptable interference cancellation (IC) scheme which combines serial (SIC) and parallel (PIC) interference cancellation to adapt to different services under different circumstances. The processing delay and computational complexity can be adjusted based on system loading and required performance. In addition to removing interference from pilot channel to traffic channel, the interferences from traffic channel to pilot channel are also cancelled. This results in better quality both on channel parameter estimation and user data detection. Compared with SIC and PIC, the proposed scheme shows better performance with reasonable hardware cost while it needs shorter processing delay than SIC.
In Chapter 5, to extend the SIC technique to turbo-coded systems, an iterative IC with ordered SIC at front-end of having good performance and low complexity is proposed. The ordering information obtained from SIC front-end is utilized in a new stopping criterion with quite low complexity and data memory to save needless iterations in turbo decoding.
From the second outer iteration, only the bits in incorrect blocks should be processed. As a
result, huge amount of computation can be saved. In addition, channel estimates from pilot-channel signal are refined from the second outer iteration with estimated traffic-channel signal removal. With the analyses in complexity and computer simulations in BER, this scheme is shown to be superior and practical in current communication systems.
Appendix A HSDPA
In Release 5, the biggest change impacting the physical layer is the addition of the high speed downlink packet access (HSDPA) to increase system throughput and deliver an improved user experience. The HSDPA is a concept to increase downlink packet data throughput by means of fast L1 retransmission and transmission combining, as well as fast link adaptation controlled by the base station (Node B).
HSDPA is fully backwards-compatible with W-CDMA, and any application developed for W-CDMA also works with HSDPA. In Release '99, individual DCH UEs have their own dedicated radio resource channels, whether they have downlink data or not. In the case of HSDPA, a wide band downlink channel can be shared among all HSDPA-capable UEs, Node B schedules to share a ”fat pipe” and can simultaneously transmit high rate data to the user with good interference/channel condition in the short term sense. Two features in WCDMA Release ‘99, variable SF and fast power control are replaced by means of adaptive modulation and coding (AMC), extensive multicode operation up to 15 multicodes in parallel and a fast and spectrally efficient retransmission strategy, named Hybrid Automatic Repeat Request (HARQ).
The retransmission procedure for the packet data is located in the SRNC in R’99. In HSDPA, the retransmission can be controlled directly by the Node B by taking into account available memory in the terminal. Fig. 2-23 presents the difference between retransmission handling with HSDPA and Release ’99. The HARQ functionality used in HSDPA can be soft combining or incremental redundancy. The former method sends the identical data as the previous transmission. The latter method transmits additional data in retransmission and has a slightly better performance with more memory required.
The Node B decides the modulation scheme and TrBk size the UE shall use or control
the transmitter power of the PhCHs of the UE for each TTI according to UE capabilities, QoS Requirements for pending data, retransmission buffer states and estimated channel quality. According to changing radio environment needs, the modulation scheme and coding rate can be quickly and flexibly modified. Both QPSK, which is used in Release ‘99, and modulation with higher capability, i.e. 16QAM, can be supported in HSDPA. The achievable theoretical maximum data rate of HSDPA can be 14.4 Mbps.
To implement the features such as fast L1 retransmission and transmission combining, as well as fast link adaptation controlled by the Node B, a new common TrCH - High Speed Downlink Shared Channel (HS-DSCH) shared by several UEs is added in HSDPA. The HS-DSCH is associated with one downlink DPCH, and one or several Shared Control Channels (HS-SCCH). The HS-DSCH is transmitted over the entire cell or over only part of the cell using e.g. beam-forming antennas. A new definition of frame structure named sub-frame is introduced in Release 5. The sub-frame is the basic time interval for HS-DSCH transmission and HS-DSCH-related signaling at the physical layer. The length of a sub-frame corresponds to 3 slots (7680 chips). The mapping of TrCH HS-DSCH onto PhCHs and its corresponding control channels are shown in Fig. 2-6.
A simple illustration of the general functionality of HSDPA is summarized in Fig. 2-25.
The Node B estimates the channel quality of each active HSDPA users. Scheduling and link adaptation are then conducted at a fast pace. Three new PhCHs are associated with HS-DSCH. The HS-PDSCH is used to carry the user data shared by several UE in the downlink from HS-DPCH. HS-SCCH carries the necessary physical layer control information to enable decoding of the data on HS-DSCH whereas the Uplink HS-DPCCH carries the necessary control information in the uplink. Fig. 2-24 illustrates the spreading operation for the Dedicated Physical Control CHannel (HS-DPCCH). The HS-DPCCH shall be spread to the chip rate by the specified channelisation code chs [74]. After channelisation,
the real-valued spread signals are weighted by gain factor βhs derived from signals from higher layers [75]. The multiplexing and coding for HS-DSCH is shown in Fig. 2-26 where the HARQ functionality after channel coding is sown in Fig. 2-27. Details of the multiplexing and coding for HS-DSCH, HS-DPCCH and HS-SCCH are described in [73].
Fig. 2-23 The difference between retransmission handling with HSDPA and Release ’99 [33]
I
j
I+jQ
Q
Shs-dpcch
chs
HS-DPCCH
(If Nmax-dpdch = 0, 1, 3, 5)
chs
HS-DPCCH
(If Nmax-dpdch = 2, 4 or 6)
βhs
βhs
Fig. 2-24 Spreading for uplink HS-DPCCH
Fig. 2-25 A simple illustration of the general functionality of HSDPA [33]
Fig. 2-26 Coding chain for HS-DSCH
Systematic bits
Parity 1 bits
Parity2 bits
RM_P1_1
RM_P2_1
RM_P1_2
RM_P2_2 RM_S
First Rate Matching Virtual IR Buffer Second Rate Matching
Nsys
Np1
Np2
Nt,sys
Nt,p1
Nt,p2 bit
separation
NTTI bit
collection Ndata
C W
Fig. 2-27 HS-DSCH HARQ functionality
Appendix B HSUPA
After introducing HSDPA, the growth of downlink traffic load reveals the shortage of uplink capacity. Mobile communications with higher data rate and shorter latency are inevitable for interactive services such as video clips sharing between users and gaming. To meet the demand, the technique so called high speed uplink packet access (HSUPA) is introduced in 3GPP Release 6. HSUPA has four key features: HARQ, fast Node B scheduling, soft handover and shorter TTI. Theoretically, the maximum peak rate is 2Mbps
in 10ms HSUPA TTI and 5.76 Mbps in 2ms HSUPA TTI.
HSUPA is expected to achieve significant improvement in overall system performance when operated together with HSDPA. HSUPA is mainly optimized for the middle or low speed (less than 60km/Hr). The uplink and downlink data transmitter have the fundamental difference in handling the total transmission power resource. In the uplink, the power amplifier capacity of a user terminal is limited, and using a higher order modulation such as 16-QAM would increase the peak to average power ratio (PAPR). Additionally, the power control cannot be abandoned in the case of continuous uplink transmission due to the near far problem. Unlike HSDPA, HSUPA use adaptive power control and also uses the same modulation method as regular WCDMA.
Scheduling is performed by Node B in order to make the Noise Rise (Signal to Noise Power) within a required level. The proper data rate is decided by Node B under the maximum rate set by RNC. When a smaller Noise Raise Margin is set, uplink capacity can be increased. UE sends control signals with rate-increasing requirement for uplink as Rate Request to Node B. Node B returns UE L1 signals as Rate Grant. Downlink control signals are Absolute Grant (AG) and Relative Grant (RG). AG means the absolute value of the power offset permitted for the power usage. Node B that controls a serving cell can send AG. RG is used as an over-load indicator to avoid larger interference and is sent from all cells in
HSUPA neighboring cells including serving cell and non-serving cells.
HSUPA neighboring cells including serving cell and non-serving cells.