Previous research has shown the characteristics of the SIC detector with binary (BPSK) and quadrature (QPSK) phase shift keying modulations [53], [54], and pipelined architecture was proposed to compensate large delay [35], [55]. In our proposed scheme, the pilot-channel signals from the received signal are cancelled before they enter next detection unit, while the respreaded estimated data are subtracted from the received signal to obtain more accurate channel parameters for further data detection. Except the coarse channel estimation used in RAKE bank for ordering at initial, all procedures are pipelined to cope with the problem of long processing delay of SIC.
4.2.1 The Proposed Scheme
We assume the n-th bit interval of the J-th user to be the bit and user of interest. For simplicity, the n-th bits of all user signals are supposed to overlap in some time interval as shown in Fig.
3-1 and all paths’ delay are perfectly estimated. From (2-3), we can observe that the data
estimates are corrupted by interference including traffic-channel signal and pilot-channel signal of other users. In order to alleviate the interference with shorter delay, we can use the proposed method as shown in Fig. 4-1. In the beginning, the coarse channel estimation are performed with a bank of PiIC #ua block. The PiIC #ua block is shown in Fig. 4-2(a). Inputs to PiIC #ua is rpi2,1(t)=r(t) while the outputs are channel estimates αu′(,nf) =αˆk(n,)f , u=k+1 where 1≤f≤F, 1≤u≤K and 0≤k<K. The channel parameters of all users are estimated with correlators followed by a moving average filter as depicted in (3-1). μk(n,l);J,p(τ) =1 occurs only when k=J and l=p and thus leads to the desired channel estimates. All the other terms of
)
) (
( ,
;
, τ
μknlJp are caused by MAI or self-interference due to multipath, while all terms of
)
) (
( ,
;
, τ
λknlJp are caused by traffic-channel signal. These interferences result in worse estimates.
At stage 1, the received signal goes through a bank of MRC RAKE receiver and the ouput ˆ( )n
Yk of user k is shown in (2-3). We choose the user with the maximum Yˆk( )n as the desired user where J=k. Fig. 4-3(a) shows the block diagram of UdIC #ua block where u denotes the cancellation order. In UdIC #1a block, the iuputs are user index J, rdia,1(t)=r(t), and
) (
,
; )
( ,
1 ˆ
~ n
f J av n
f α
α<> = in (3-1) where 1≤ f ≤F, and the corresponding outputs are data decision
~ } sgn{
]
~ [ ( )
1 n
YJ
n
b<> = where ~(n)
YJ is obtained from (2-3), the respreaded data ~ ( )
1
; t
Cdata<>
and the remained received signal rdo1a,1(t) and rdo2a,1(t) where
)
~ ( )
~ ( ) ( )
( ; 1 ;1
1 ,
1 t r t C t C t
rdo a = − pilot<> − data<>
(4-1)
)
~ ( ) ( )
( ; 1
1 ,
2 t r t C t
rdo a = − data<>
(4-2)
⎣ ⎦ [
⎣
( )/⎦
] ( ) where <1> means the first cancelled user.Inputs to the PiIC #un block as shown in Fig. 4-2(b) at stage 1 are user index J, ) in stage 2 to find the user with maximum power. Signal without pilot-channel interference from PiIC block of the 1st user, rpo,1(t), is sent to UdIC #1b block, this time we use refined channel parameters instead of coarse channel parameters.
For the UdIC #1b block shown in Fig. 4-3(b), inputs are user index J, rdib,1(t)=rpo,1(t), and α<(1n>),f =αJ′(,nf) where 1≤f≤F, and the corresponding outputs are data decision
}
For the n-th bit interval signal at the u-th stage, relation among all the above signals can be written as follows. From u>1, for UdIC #ua block,
)
)
rdibu . The process repeats until all K user data are detected.
4.2.2 Computational Complexity Analysis
In Fig. 4-1, we can find that there are two more blocks per stage in the proposed scheme in comparison with SIC II in Chapter 3, i.e. PiIC #b unit and UdIC #b blocks. Although the hardware complexity increases, the throughput is K times the normal SIC and the latency only increases with the time spent for signal processing through PiIC unit and UdIC one
time. Table 4-1 lists the computational complexity analysis. In the following, it is shown that the extra blocks in our proposed scheme can help to achieve better performance than other interference cancellation schemes and RAKE receiver.
4.2.3 Simulation Results and Discussions
The simulation parameters are the same as those in Table 3-2 except that the βc=1, G=1 bit and PDR= . We simulate four kinds of detectors with multipath fading channel Case 3 1 in Table 3-3 and total power of all paths are normalized to unity. A 4-finger rake receiver is used for path combination. The path delay is assumed to be perfectly known. Fig. 4-4 shows performance comparison among the proposed pipelined scheme, rake receiver, SIC without pilot signal remover, and PPIC [22] with coefficient 0.6 at the first stage under different users.
At the same BER, the proposed method has larger user capacity. Besides, note that the proposed scheme performs better at SNR=10dB than SIC at SNR=15dB when there are more than about 10 users in the system. Thus, we can achieve the same BER at lower SNR by using the proposed scheme..Fig. 4-5 shows the performance of detectors under different SNRs. We can find that the proposed scheme performs slightly better than SIC at low SNR while it performs much better than any other scheme in the simulation when the SNR is high. The reason is that the noise term dominates the system performance at low SNR while the interferences we dealt with between different users and paths play a relatively important role at high SNR. Besides, channel parameters can be estimated precisely when data interferences are eliminated at high SNR. Therefore, the proposed scheme is recommend for interference cancellation at higher SNR as a result of hardware complexity.