Architecture for 8-bit 40MHz ADC

2.3.1 Architecture [4][5]

The block diagram of a typical pipelined ADC is shown in Fig. 2.6. All of the pipelined stages are similar in structure. Each stage consists of a sample-and-hold amplifier, a Digital-to-Analog converter (DAC), a low resolution Analog-to-Digital sub-converter (ADSC), a subtractor, and a fix-gain amplifier. The beginning sample-and-hold relaxes the timing requirements of the first stage during its sampling phase by holding the instantaneous value of the analog input. Following the S/H, each stage samples and holds the output signals of the previous stage. The signal is coarsely quantized by the ADSC to produce the first 1 MSB’s and 1 bit for digital error correction. Then using a DAC, the quantized value is subtracted from original input signal to yield the output residue. For the output signal range is the same with the input signal range for each stage, this is made by the amplifier with gain of 2. The resulting residue signal is applied to the next stage for finer conversion on the next clock cycle. The function of the D/A, the subtraction, and the amplification of the remainder are combined into one single circuit called the multiplying DAC (MDAC). The last stage consists of a 2-bits flash ADC, and a thermometer-code-to-binary-code combinational logic.

Fig. 2.6 Architecture of 8-bit Pipeline ADC

After the signal has propagated through 8 stages, one complete conversion is produced. The total digital outputs from all stages are 14 bits. These operations work concurrently and enable the pipelined architecture to achieve a high throughput. The digital codes ate overlapped by 1 bit to perform digital error correction. Therefore, the total 14 bits from all stages are delayed properly and produced 8 bits [6][7]. Although a single-ended configuration is shown for simplicity, the actual implementation was fully differential.

The conceptual circuit of main stages of pipeline is shown in Fig. 2.7. The MDAC with SC configuration performs sample-and-hold function, DAC, subtraction and multiply by 2 functions. The ADSC consists of two flash converters. The input is sampled by the frontier S/H circuit to convert the analog signal to the two differential dc signal input. Then, the signal is compared by two comparators to decide where it is located on the residue chart. The decision level is ±1/4Vr (Vr: full swing of input voltage). The output digital codes are latched by the D-flip-flop which is used for doing pipeline. Because each stage’s output does not come out at the same time, we have to use flip-flop to latch them. From Fig.2.7, we can realize that the MDAC only needs to decide 3 conditions 2Vin-Vr, 2Vin, or 2Vin+Vr. The MDAC’s output is the next stage’s input. When the input signal is applied, each stage samples and quantizes, subtracts the quantized analog output signal of DAC, and passes the residue to the next stage with amplification for finer conversion. Every stage can get 2-bit digital output

00, 01 and 10, and be latched in to the pipeline path.

Fig 2.7 Main Stage Circuit and Transfer Curve

2.3.2 Timing Strategy

The design of our residue amplify circuit is a switch-capacitor S/H structure as shown in Fig.2.8. The basic ideal of switch-capacitor circuit is the charge transfer. The important issue is to transfer the charge totally without loss. Thus, two non-overlap clock phases clk1 clk2 are required. In order to cancel out the charge injection error, the fully differential structure and the bottom-plate technique is used in the residue amplify circuit. This will need two more advanced clock phases clk1p clk2p. For example, the clk1p control the switches on the top-plate of sample capacitors and turn off earlier before the switches on the bottom-plate so that the charge injection is signal independent. The addition phases, clk1a and clk2a, are needed for the ASDC. To avoid the noise being compared by comparators in the beginning of transferring, the comparator will start comparing until the charge redistribution has been finished and stabilized. The waveform is shown in Fig. 2.8.

Fig. 2.8 Clock Waveform

2.3.3 Digital Error Correction

Digital error correction is the name of the calibration technique that reduces the gain, keeps the voltage range constant with modified coding and tolerates greater comparator offset. A conceptual transfer function is shown in Fig.2.9. This kind of digital error correction is called the 1.5bit/stage algorithm. The comparator thresholds (ADSC) are at 1/4Vr and -1/4Vr; the DAC levels are at -1/2Vr, 0 and 1/2Vr. The codes are shown on top of the transfer function and the over-ranging part on the transfer function will be digitally corrected by the next stage except the last stage of the pipeline. The 1.5-bit/stage here represents the effective bits per stage after digital correction [8]. We can get 2-bit in each stage. The second bit is used for correction. When the input is less than the negative decision level, -1/4Vr, we simply get a 0 in the first bit and give another 0 in the second bit. The second bit is 0 means that no need to add 1 to the first bit. In the same way, when the input is greater than the positive decision level, +1/4Vr, we can get a 1 in the first bit and give another 0 in the second bit, meaning that

no need to get a 1 in the first bit and give another 0 in the second bit. When the input is in the un-distinguished region between -1/4Vr and +1/4Vr, we give a 0 in the first bit and give a 1 in the second bit. We can get 0 in this stage and residue is 2xVin. In the next stage, if the input is positive, then the first bit will be corrected because it will get a “10”. If the input is negative, then the next stage will get a “00”. And there is no need to change the “0” bit in the first stage.

The amplified residue remains within the conversion range of the next stage when the ADSC nonlinearity is between . Under these conditions, errors caused by the ADSC nonlinearity less than 1/2 LSB can be corrected. For example, see from Fig.2.9 when the input is in the “10” region and very close to the “01” region. If the comparator is wrong and decides the input as “01”. Then it will produce a residue of 2Vin. The residue voltage is the same as the real value, that it won’t affect the next few stages. And we can correct this bit by adding one to “01”.

LSB 2 /

±1

Fig. 2.9 Example of Digital Error Correction: First Stage to Next Stage