Sample-and-Hold

The most important and performance dominating circuit in the pipelined ADC is the input stage sample-and-hold (S/H) amplifier. Fig.3.1 shows the schematic diagram of the unity-gain S/H. The signal ground Vmid is the common-mode voltage of the output differential signal.

The architecture of the op-amp is a telescopic amplifier, which has an input common-mode voltage at 1.2V and an output common-mode voltage at 1.5V. The clock1, clock1p are used during the sample phase and clock2 is used during the hold phase. The clock1 and clock2 are non-overlap phases to prevent the charge loss on the path when both the clocks are at high level. The clock1p has the same rising edge to the clock1 phase, but the earlier falling edge takes the advantage of reducing the charge injection from the sampling switches. There is a switch connects output nodes during the sample phase, and then keeps the voltage of output nodes at the output common-mode and prevent saturation. That reduces the settling time when a non-saturated voltage needs to go back to the target voltage at hold phase.

Fig.3.1 Schematic diagram of sample-and-hold

3.1.1 Capacitors [11]

A certain minimum signal capacitor size is needed to maintain adequate noise performance and dynamic range. The SNR (signal to noise ratio) is calculated as

⎟⎟

where VR is the analog signal range and VN is the effective noise voltage. VN is mainly introduced by two components, one is the quantization noise and the other is thermal noise.

The quantization noise of a sine wave input is . The thermal noise is calculated as 3KT/C where one KT/C is introduced when a switch opens into a charge sampling capacitor, one KT/C is introduced when a switch opens into a charge holding capacitor, and the other one KT/C is introduced by all the possible noise sources.

12 / ) (LSB ²

By the MATLAB simulation, we can know that the SNR will be dominated by the quantization noise when the size of capacitor is from 0.1p-1p. Capacitor is found that satisfies the bandwidth requirements, capacitor matching requirements, and KT/C noise constraints. If the size is too large, the op-amp might not be able to reach the required speed. If the size is too small, the clock feed-through and charge-sharing effect will be worse. In this design, the Cs is 500fF.

3.1.2 Op-amp Gain Requirement

The DC open-loop gain of the op-amp limits the ADC resolution. Fig.3.2 simplified the S/H circuit. The capacitor Cp is the parasitic capacitor of the op-amp input differential pair.

To predict the required gain of the op-amp which makes Vout in the acceptable range of Vin.

From the circuit setup, we have

−

The fractional error is approximately^1/( )^Af . In this design, for an 8-bit ADC, the Vout of S/H constitutes the input of the following 8 stages. If the maximum tolerable DNL is 0.5 LSB at 8 bit level for the following 8 stages, then ^1/

( )

( )

29

1 ×

≥ f

A (5)

We can derive that the required A is 54.18dB when Cp is zero, 60.2dB when Cp=Cs, and 55.77dB when Cp Cs

5

=1 .

Fig.3.2 Op-amp gain requirement

3.1.3 Op-amp Bandwidth Requirement

The settling time of the op-amp limits the ADC conversion speed. For more strict consideration of bandwidth requirement, we predict that the settling period is separated into two parts: slew-rate limited transient response and time constant limited transient response.

Briefly we can assume the time ratio of the two parts to be 1/3. That would be 2.5ns:7.5ns in our timing arrangement. Fig.3.3 shows the timing arrangement in half cycle. During the slew-rate (SR) limited transient response period, the critical case will be full range swing in 2.5ns. We can calculate the requirement of slew-rate as

us

unity-gain frequency of op-amp. Take the single pole system for consideration,

Therefore, the settling time of the single pole system is given by the formula below.

u

So that the minimum slew-rate is 200V/us and the minimum unity gain frequency is 159MHz which f (feedback factor) is 5/6 and N is 8-bit in the front end S/H stage.

Fig.3.3 Settling time of S/H

3.1.4 Switches

The switch used in the sample-and-hold circuit in sample mode is shown in Fig.3.4. The Ron is independent of the input voltage Vin if we choose the complementary switches. It enhances the SNR and the linearity of the pipeline ADC. The voltage in the input of op-amp almost doesn’t change when the switches S1 turn on. So using the NMOS transistor only will be suitable.

The speed of the sampling circuit is another important factor to influence the harmonic distortions of a pipeline ADC. Generally speaking, the switches and capacitors can be considered a RC network, the noise comes with input signal will be filtered out more or less.

To avoid the input signal being depressed by the RC network, it is necessary to make sure the bandwidth of the RC network far from the data rate. In another point of view, take the single pole system for consideration, the RC time constant should be able to reach the requirement of equation (9). We select R=1k Ron=0.1k for the trade-off of clock feed-through and charge injection [12].

Fig.3.4 Switches of S/H in sample mode